PCIe Dev Kit Stratix II GX and the TSE MegaCore

At this point I would do two things:

1 - Check the timing analysis. Is the Ethernet interface fully constrained?

2 - Make sure the simple socket server example is set to use DHCP. Use a packet sniffer like wireshark to see if the board is sending anything out on the wire at startup.

Jake

Oh one other thing. Is the phy getting a proper reset on initialization?

Jake

Hi Lerxt and Jacobjones,

I am brand new on this forum, and I am trying to do quite the same type of thing as you are doing, Lerxt, implementing a simple socket server on the SIIGx PCIe board. I am more or less at the same point as you are, so I checked your code and I was wondering about the source clock you are using: shouldn't you use a 100MHz clock instead of the 156.25 Xaui one? On my side, I am using the 100MHz LVDS clock delivered to the SIIGx on A20/A21 pair.

I'll let you know if I manage to make my simple socket server work as well.

Sophie

Thanks, Sophie, now I am using the PIN_A20 in the TSE core, and PIN_H7 to the rest of design.

The only thing that Reference Manual says about the 100 MHz clock is they are localized in pins 4 and 5. But where is the pin 4 and 5?

But it didn't work yet.

I don't know how I reset the PHY, because I don't have any pin for it.

When I set the simple socket server to use the DHCP, the Marvell PHY waits a reset =/

Which modification I have to do to reset PHY in my design, jakobjones?

Hi Lerxt,

the pins 4 and 5 refer to the 100MHz oscillator mounted on the board. You can use the schematics delivered with the board to follow the path of the signals (the file is s2gxpcie.pdf, very useful).

I think as well that you should connect the tx_clk and rx_clk to the phy.

For the reset, you can internally connect the fpga reset to the phy_reset (pin H31).

Sophie

Hi, Sophie,

I didn't know that file (s2gxpcie.pdf), it is very useful.

I connected the rx_clk and tx_clk to PIN_M27 and PIN_F28 respectively.

The source_clock is now connected to PIN_A20.

And I created a input pin, called reset_phy (PIN_AM22). It is connected with the output pin called enet_resetn (PIN_H31).

But it didn't work yet.

I will use the Signal Tap to see what is happen with tx_clk, rx_clk, rx_d[7..0] and tx_d[7..0].

I will try to export my design to Quartus 8.0 and try something similar to this:

http://www.alteraforum.com/forum/showpost.php?p=13292&postcount=17

I've already started to ask help from Altera...

Did you have any progress, Sophie?

Hi Lerxt/Sophie,

I am also trying to do something similar to you guys.

Lerxt: When I try to open your core.zip project in Quartus II (8.0) I get many errors related to eth_ocm_0 not being found.

Specifically, when I try to do a Full Compilation I get:

Error (10054): Verilog HDL File I/O error at eth_ocm.v(247): can't open Verilog Design File "eth_defines.v"

Error (10054): Verilog HDL File I/O error at eth_ocm.v(248): can't open Verilog Design File "timescale.v"

Error (10112): Ignored design unit "eth_ocm" at eth_ocm.v(251) due to previous errors

Also, when I open up SOPC, the eth_ocm_0 module is highlighted in red, and says "Missing Module" next to it.

Do you know anything about this?

Thanks,

JB

For those that may be trying to do the same thing, I just deleted the eth_ocm component in SOPC Builder and the design compiled without a problem.

After doing some further research, though, it appears that the eth_ocm was an old component replaced by the tse_mac. The design files (and more details) can be found here: http://www.niosforum.com/pages/project_details.php?p_id=115&t_id=18.

JB