PCIe Dev Kit Stratix II GX and the TSE MegaCore

Hi Lerxt/Sophie,

I am also trying to do something similar to you guys.

Lerxt: When I try to open your core.zip project in Quartus II (8.0) I get many errors related to eth_ocm_0 not being found.

Specifically, when I try to do a Full Compilation I get:

Error (10054): Verilog HDL File I/O error at eth_ocm.v(247): can't open Verilog Design File "eth_defines.v"

Error (10054): Verilog HDL File I/O error at eth_ocm.v(248): can't open Verilog Design File "timescale.v"

Error (10112): Ignored design unit "eth_ocm" at eth_ocm.v(251) due to previous errors

Also, when I open up SOPC, the eth_ocm_0 module is highlighted in red, and says "Missing Module" next to it.

Do you know anything about this?

Thanks,

JB