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Altera_Forum
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17 years ago

PCIe Dev Kit Stratix II GX and the TSE MegaCore

Hi everyone, I'm new here and have a question. By the way, it's my first adventure with complex cores and FPGA's, I used to programming in ARM before that. I want to run a aplication on Nios II ...
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Altera_Forum
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17 years ago

Hi, Sophie,

I didn't know that file (s2gxpcie.pdf), it is very useful.

I connected the rx_clk and tx_clk to PIN_M27 and PIN_F28 respectively.

The source_clock is now connected to PIN_A20.

And I created a input pin, called reset_phy (PIN_AM22). It is connected with the output pin called enet_resetn (PIN_H31).

But it didn't work yet.

I will use the Signal Tap to see what is happen with tx_clk, rx_clk, rx_d[7..0] and tx_d[7..0].