PCIe Dev Kit Stratix II GX and the TSE MegaCore

Hi folks.

I guess I'm in the right way.

I had to change the Cypress SRAM memory by a DDR2.

Now the problem is how to configure the DDR2 on PCIe Dev Kit...

I downloaded the software in the FPGA, but i tried to download the Simple Socket Server example, but I couldn't. It showed this menssage:

"Verify failed between address"

If I fix that problem, I will post the project here...

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Hi everyone, I'm new here and have a question.

By the way, it's my first adventure with complex cores and FPGA's, I used to programming in ARM before that.

I want to run a aplication on Nios II catching packages from the Ethernet interface (RJ-45).

The first problem is I don't have any example for that board which uses the RJ-45 interface, 'cause I don't have the SFP conector yet.

I want to adapt this core here (Small TSE MAC Ethernet Example - http://nioswiki.jot.com/small%20tse%20mac%20ethernet%20example) to use it in a PCIe Dev Kit with Stratix II GX. But it requires a SSRAM, but the Stratix II GX don't use this kind of memory.

Can any one here help me?

Thanks!

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I suggest you use simple socket server (depending upon your application, you can also convert it to a "simple socket client") example as your apllication requires reception of data only. Can you write what exactly that SSRAM doing in this example? If it is an external RAM, you can always replace it with any other RAM that is available to you.

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Hi folks.

I guess I'm in the right way.

I had to change the Cypress SRAM memory by a DDR2.

Now the problem is how to configure the DDR2 on PCIe Dev Kit...

I downloaded the software in the FPGA, but i tried to download the Simple Socket Server example, but I couldn't. It showed this menssage:

"Verify failed between address"

If I fix that problem, I will post the project here...

--- Quote End ---

When you get "Verify failed between address" message, just check the address range in that. You can then find out exactly which component is not working (though this error usually indicates problem with boot_flash).

I would like to start this by thanking for your response,Vizziee.

I'm trying to use the PCIe Dev Kit to capture Ethernet packages to process it in the NiosII using 1 GBs' interface, via RJ-45, and in the future using the optical interface.

But, to make it in that board I think that I need this basic architecture:

NiosII -> DDR2 -> SGDMA -> TSE -> (RJ-45 or SPF)

In that board I have those memories: MT47H32M16CC-3 32Mx16 and a MT47H64M8CB-3 32Mx8.

In Cyclone II Dev Kit is more simple, because I can use a Cypress SRAM, that is more simple than the these ones.

I made what you said and discovered the "Verify failed between address" was in DDR2 memory section.

I'm using the an517 tutorial, making the modifications to PCIe Dev Kit, and now I have this problem:

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Using cable "USB-Blaster [USB-0]", device 2, instance 0x00

Pausing target processor: not responding.

Resetting and trying again: FAILED

Leaving target processor paused

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PS: I didn't connect the TSE module yet, I'm just trying to configure the DDR2 correctly first.

Altera says this abou this erro:

http://www.altera.com/support/kdb/solutions/rd07272007_849.html

But I realy don't know...

Lerxt,

Your first error was received because the NIOS IDE attempted to download your application code to the memory that you specified as your program memory in the system library settings. However, after it tried to download, it attempted to verify that the memory was programmed correctly and failed.

This probably occurred because your DDR2 interface is not operating correctly. Could you please post a screenshot of your SOPC builder system?

Your second error usually occurs for one of two reasons:

1 - Your clock or reset connection to your processor is stuck.

2 - Your clock or reset connection to your DDR2 interface is stuck. This one is less obvious. I assume you are using a clock crossing bridge between your NIOS processor and the DDR2 memory. If the DDR2 interface clock is stuck, the FIFO within the clock crossing bridge never gets emptied which results in a waitrequest signal being permanently asserted to the NIOS' Avalon master. Then the system hangs.

The fix for the second error is to just make sure everything is connected properly, your clocks are running as they should be, and your reset signals aren't stuck active.

Jake

It's working now, vizziee and jakobjones, I only decreased the clock to make it work correctly.

Now I will integrate with TSE core.

In the Lybaries Settings I was specifying the on-chip memory as my program memory, jakobjones.

Yesterday, I was going to post the qar file and the screenshots here, but my machine suddenly died and my project folder was deleted (I should use SVN next time).

Then, next week I will remake the project and post it here.

Cheers,

Lerxt

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I'm using the an517 tutorial, making the modifications to PCIe Dev Kit, and now I have this problem:

PS: I didn't connect the TSE module yet, I'm just trying to configure the DDR2 correctly first.

Altera says this abou this erro:

http://www.altera.com/support/kdb/solutions/rd07272007_849.html

But I realy don't know...

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While the Altera's explanation is more towards software, there is a high chance that you got this error as Nios was unable to get a clock signal. Check if the clock connection to board/FPGA is fine.

Sorry for the delay, I promised that it would post the project when the DDR2 was working.

I still have problems with the TSE module...

I think that is the timing constraints or there's something wrong with design...

I don't know how to correctly use the Time Quest :(.

I receive this in the Simple Socket Server:

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nios2-terminal: connected to hardware target using JTAG UART on cable

nios2-terminal: "USB-Blaster [USB-0]", device 2, instance 0

nios2-terminal: (Use the IDE stop button or Ctrl-C to terminate)

=============== Software License Reminder ================

This software project uses an unlicensed version of the NicheStack TCP/IP

Network Stack - Nios II Edition. If you want to ship resulting object

code in your product, you must purchase a license for this software from

Altera. For information go to: "http://www.altera.com/nichestack"

=====================================================

InterNiche Portable TCP/IP, v3.0

Copyright 1996-203 by InterNiche Technologies. All rights reserved.

prep_tse_mac

Could not locate flash sector with MAC address.

Static IP Address is 192.168.0.200

prepared 1 interface, initializing...

[tse_mac_init]

SGDMA desc memory cleared

[phyID] 0x12 141 cc2

[netif_tse] found Marvell 88E1111 PHY

Speed is 1000 is 0 Full Duplex is 1

OK, x=1, CMD_CONFIG=0x00000000

MAC post-initialization: CMD_CONFIG=0x04000203

[tse_sgdma_read_init] RX descriptor chain desc (1 depth) created

IP address of et1 : 192.168.0.200

Created "Inet main" task (Prio: 2)

Created "clock tick" task (Prio: 3)

Simple Socket Server starting up

[sss_task] Simple Socket Server listening on port 30

Created "simple socket server" task (Prio: 4)

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I never saw the TX led blinking :confused:, and why I receive this: " Speed is 1000 is 0 Full Duplex is 1".

Actually according to the messages, you have no errors. These are all normal printout messages from the triple speed ethernet MAC. In fact, the MAC driver is stating that it was able to detect the PHY chip on the board which is good. You are at least communicating with the PHY. The statement:

Speed is 1000 is 0 Full Duplex is 1

is informing you that the PHY and MAC are configured for Full Duplex Non-Gigabit operation.

Now this doesn't necessarily mean things are working. Have you tried to ping the board?

Jake

Yes, but I get time out.

I think that leonchang0000 (http://www.alteraforum.com/forum/member.php?u=6116) had a similar problem:

http://www.alteraforum.com/forum/showthread.php?t=3210&highlight=ethernet+stratix

But in my case, it is in a PCIe Dev Kit SIIGX.

I will try to ask how he fixed his design.