Altera SOPC Builder Version 7.20 Build 203
Copyright (c) 1999-2007 Altera Corporation.  All rights reserved.


# 2008.11.04 14:40:04 (*) mk_custom_sdk starting
# 2008.11.04 14:40:04 (*) Reading project C:/workspace/ethernet/core/ethernet.ptf.

# 2008.11.04 14:40:05 (*) Finding all CPUs
# 2008.11.04 14:40:05 (*) Finding all available components
# 2008.11.04 14:40:05 (*) Reading C:/workspace/ethernet/core/.sopc_builder/install.ptf

# 2008.11.04 14:40:05 (*) Found 70 components

# 2008.11.04 14:40:07 (*) Finding all peripherals

# 2008.11.04 14:40:07 (*) Finding software components

# 2008.11.04 14:40:08 (*) (Legacy SDK Generation Skipped)
# 2008.11.04 14:40:08 (*) (All TCL Script Generation Skipped)
# 2008.11.04 14:40:08 (*) (No Libraries Built)
# 2008.11.04 14:40:08 (*) (Contents Generation Skipped)
# 2008.11.04 14:40:08 (*) mk_custom_sdk finishing

# 2008.11.04 14:40:08 (*) Starting generation for system: ethernet.

..
.
.
.
.
...
..
.
.......
...

# 2008.11.04 14:40:11 (*) Running Generator Program for descriptor_memory

# 2008.11.04 14:40:16 (*) Running Generator Program for dma_read_memory

# 2008.11.04 14:40:19 (*) Running Generator Program for cpu

# 2008.11.04 14:40:23 (*)   Checking for plaintext license.
# 2008.11.04 14:40:23 (*)   Plaintext license not found.
# 2008.11.04 14:40:23 (*)   Checking for encrypted license (non-evaluation).
# 2008.11.04 14:40:24 (*)   Encrypted license not found.  Defaulting to OCP evaluation license (produces a time-limited SOF)
# 2008.11.04 14:40:27 (*)   Master tightly_coupled_instruction_master_0 address range (0x6040000, 0x604ffff) overlaps with master instruction_master address range (0x4000000, 0x6062fff)
# 2008.11.04 14:40:27 (*)   Master instruction_master address range (0x4000000, 0x6062fff) overlaps with master tightly_coupled_instruction_master_0 address range (0x6040000, 0x604ffff)

# 2008.11.04 14:40:27 (*)   Generating non-optimal tightly-coupled master logic due to overlap
# 2008.11.04 14:40:27 (*)   Master tightly_coupled_data_master_0 address range (0x6050000, 0x605ffff) overlaps with master data_master address range (0x2000000, 0x6063f87)
# 2008.11.04 14:40:27 (*)   Master data_master address range (0x2000000, 0x6063f87) overlaps with master tightly_coupled_data_master_0 address range (0x6050000, 0x605ffff)
# 2008.11.04 14:40:27 (*)   Generating non-optimal tightly-coupled master logic due to overlap

# 2008.11.04 14:40:39 (*)   Creating encrypted HDL

# 2008.11.04 14:40:43 (*) Running Generator Program for jtag_uart

# 2008.11.04 14:40:47 (*) Running Generator Program for pio

# 2008.11.04 14:40:50 (*) Running Generator Program for dma

# 2008.11.04 14:40:51 (*)   dma: allowing these transactions: word, hw, byte

# 2008.11.04 14:40:54 (*) Running Generator Program for altmemddr

# 2008.11.04 14:40:55 (*) Running Generator Program for sgdma_rx

# 2008.11.04 14:41:00 (*) Running Generator Program for sgdma_tx

# 2008.11.04 14:41:05 (*) Running Generator Program for sys_clk_timer

# 2008.11.04 14:41:08 (*) Running Generator Program for high_res_timer

# 2008.11.04 14:41:11 (*) Running Generator Program for ext_flash

# 2008.11.04 14:41:14 (*) Running Generator Program for packet_memory

# 2008.11.04 14:41:17 (*) Running Generator Program for cpu_converter

# 2008.11.04 14:41:20 (*) Running Generator Program for cpu_vector

# 2008.11.04 14:41:24 (*) Running Generator Program for tci

# 2008.11.04 14:41:27 (*) Running Generator Program for burst_0

# 2008.11.04 14:41:31 (*) Running Generator Program for burst_1

# 2008.11.04 14:41:35 (*) Running Generator Program for burst_2

# 2008.11.04 14:41:39 (*) Running Generator Program for burst_3

# 2008.11.04 14:41:42 (*) Running Generator Program for burst_4

# 2008.11.04 14:41:46 (*) Running Generator Program for burst_5

.

# 2008.11.04 14:41:50 (*) Running Test Generator Program for altmemddr

# 2008.11.04 14:41:52 (*) Making arbitration and system (top) modules.

# 2008.11.04 14:42:35 (*) Generating Quartus symbol for top level: ethernet

# 2008.11.04 14:42:35 (*) Symbol C:/workspace/ethernet/core/ethernet.bsf already exists, no need to regenerate
# 2008.11.04 14:42:35 (*) Creating command-line system-generation script: C:/workspace/ethernet/core/ethernet_generation_script

# 2008.11.04 14:42:36 (*) Running setup for HDL simulator: modelsim


# 2008.11.04 14:42:36 (*) Setting up Quartus with ethernet_setup_quartus.tcl
c:/altera/72/quartus/bin/quartus_sh -t ethernet_setup_quartus.tcl


Info: *******************************************************************
Info: Running Quartus II Shell
    Info: Version 7.2 Build 203 02/05/2008 Service Pack 2 SJ Full Version
    Info: Copyright (C) 1991-2007 Altera Corporation. All rights reserved.
    Info: Your use of Altera Corporation's design tools, logic functions 
    Info: and other software and tools, and its AMPP partner logic 
    Info: functions, and any output files from any of the foregoing 
    Info: (including device programming or simulation files), and any 
    Info: associated documentation or information are expressly subject 
    Info: to the terms and conditions of the Altera Program License 
    Info: Subscription Agreement, Altera MegaCore Function License 
    Info: Agreement, or other applicable license agreement, including, 
    Info: without limitation, that your use is for the sole purpose of 
    Info: programming logic devices manufactured by Altera and sold by 
    Info: Altera or its authorized distributors.
  Please refer to the 
    Info: applicable agreement for further details.
    Info: Processing started: Tue Nov 04 14:42:36 2008
Info: Command: quartus_sh -t ethernet_setup_quartus.tcl
Info: Evaluation of Tcl script ethernet_setup_quartus.tcl was successful
Info: Quartus II Shell was successful. 0 errors, 0 warnings
    Info: Allocated 44 megabytes of memory during processing
    Info: Processing ended: Tue Nov 04 14:42:36 2008
    Info: Elapsed time: 00:00:00

# 2008.11.04 14:42:38 (*) Completed generation for system: ethernet.
# 2008.11.04 14:42:38 (*) THE FOLLOWING SYSTEM ITEMS HAVE BEEN GENERATED:
  SOPC Builder database : C:/workspace/ethernet/core/ethernet.ptf 
  System HDL Model : C:/workspace/ethernet/core/ethernet.v 
  System Generation Script : C:/workspace/ethernet/core/ethernet_generation_script 

# 2008.11.04 14:42:38 (*) SUCCESS: SYSTEM GENERATION COMPLETED.


Press 'Exit' to exit.
