Need help creating a simple 32bit counter

Thats the reason why i stay with verilog HDL as VHDL has so much typo for such simple stuff.

module counter_example { CLK, OUT1 Q };

input CLK;

output OUT1;

output [31:0] Q;

always @ ( posedge CLK )

Q <= Q + 1; // or write 32'd1 to avoid warnings due to truncation

always @ ( posedge CLK )

OUT1 <= CLK;

endmodule // thats it

stepping trough like c code, haven't seen that even on our SUN used for ASIC designs with much much more expensiv tools ($$$ per year)

The edge sensitive condition is missing. See the VHDL templates in Quartus editor for the basic syntax of clock synchronous logic.

Although VHDL is a hardware description language rather than being executed line by line like a C program, you can single step it in a simulator as ModelSim, that is interpreting the VHDL text in this place.

Thanks, a friend suggested verilog over VHDL, maybe I should listen to him.

Question: The following works

Q    : buffer  std_logic_vector(31 downto 0));
    if CLK'EVENT AND CLK = '1' then
        Q <= Q + 1 ;
    end if;

But if the counter is stored in a variable and copied to Q on a positive edge it doesn't work.

ie:

    if CLK'EVENT AND CLK = '1' then
        counter := counter + 1;  
        Q <= counter ;
    end if;

Why doesn't that work?

First off, welcome to VHDL.

2nd. There is a reason it is not updating with the variable and its all down to how the language works. You should find that if you swap around the counter + 1 statement and the q <= counter statement (so the Q output is set first) it will work.

This is because variables are updated immediately, whereas signals are not. The code you currently have will work in a simulator, but when you synthesise it, as the variable is used to assing a value to Q, there is no need to store the value in counter between clock cycles (because you have stored the value in Q. Now if you swapped the 2 statements around to this:

if CLK'EVENT AND CLK = '1' then
Q <= counter ;        
counter := counter + 1;           
end if;

The synethsiser notes that counter is not assigned to a register at the end of the process, but you do give the value to Q before you increment it, so it will create one for you to store the value of counter between clocks. Like I said before, either way round will work in simulation, but not in synthesis.

3rdly. As you are new to VHDL please can I ask you to stop using std_logic_unsigned/arith now, and use the IEEE standard instead, which is numeric_std, so you dont get into bad (or old fashioned) habits. You can also use rising_edge(clk) instead of clk'event and clk = '1', as it is slightly safer to use in simulation. The rising_edge function will only trigger when the clk signal changes from '0' or 'L' to '1' or 'H', whereas the latter will trigger whenever the clk signal changes from anything to '1' (so 'X', 'U', '-', '0', 'Z', 'H', 'L').

the numeric_std library offers the signed and unsigned types which you can use in the same file (with the std_logic_unsigned/signed you cannot use both types at the same time). You could also do this counter simply by doing this:

signal counter : unsigned(31 downto 0);
.....
process(clk)
begin
  if rising_edge(clk) then
    counter <= counter + 1;
  end if;
end process;
Q <= std_logic_vector(counter);

Another thing to keep in mind is that port lists only HAVE to be std_logic/vector at the top level, theres nothing to stop you using integers, unsigneds, booleans, fixed point types in the port definition of an entity.

You should show complete library and signal/variable definition.

Generally, this code is supposed to work. But possibly, you found a way to thwart it.

    if CLK'EVENT AND CLK = '1' then
        counter := counter + 1;  
        Q <= counter ;
    end if;

--- Quote Start ---

You should show complete library and signal/variable definition.

Generally, this code is supposed to work. But possibly, you found a way to thwart it.

    if CLK'EVENT AND CLK = '1' then
        counter := counter + 1;  
        Q <= counter ;
    end if;

--- Quote End ---

Like I said, it thwarts the synthesisor because there it sees no point in registering counter, because it registers Q instead. Because counter never read's back from Q, counter is always assumed to be 0.

The best way to fix it and make it synethsise is swap the 2 statement, or do this instead:

    if CLK'EVENT AND CLK = '1' then
  counter := Q;
  counter := counter + 1;  
  Q <= counter ;
  end if;

Thanks Tricky, that got me up and running :)

Does verilog operate the same way in relation to instruction flow and signal vs variable? Also is there a good source for these idiosyncrasies in the language?

In an unrelated question every time I recompile I need to goto

Tools -> Simulator Tool -> Generate Functional Simulation Netlist

to run a simulation, is there a way to automatically generate the netlist or am I doing something wrong?

--- Quote Start ---

Thanks Tricky, that got me up and running :)

Does verilog operate the same way in relation to instruction flow and signal vs variable? Also is there a good source for these idiosyncrasies in the language?

In an unrelated question every time I recompile I need to goto

Tools -> Simulator Tool -> Generate Functional Simulation Netlist

to run a simulation, is there a way to automatically generate the netlist or am I doing something wrong?

--- Quote End ---

I do not know anything about verilog, though the words blocking and non-blocking assignments has been used before to equate signals and variables in VHDL from time to time.

for the 2nd point you're simulating a post-P&R netlist, which will be slow (but will function as it would on real hardware). In modelsim you can simulate your VHDL text files directly with no synthesis required. You will need to create a testbench to stimulate all of the inputs (like generating a clock) but thats quite straight forward.

To generate a clock in a VHDL testbench you can just use the line:

signal clock : std_logic := '0';
clk <= not clk after 10 ns; --will give 50MHz clock

and then just connect the clock to the clk port on your counter.

in verilog you can use blocking and non blocking assignments, you can mix them but you need to decide which one you use inside an always block for this particular block

non blocking

q <= counter;

counter <= counter + 1;

is the same as if you swap the lines

counter <= counter + 1;

q <= counter;

both work the same way.

but if you use blocking assignments then it does matter in which order you write your code.

i personaly use non blocking assingments as ther are enough bugs around to catch ...

I found the "Start Compilation and Simulation" option in Quartus which saves a few steps, however I thought I'd try setting up a test bench. I installed ModelSim, when I run the simulation and look in wave I can see the clock but counter_out has no value. Did I set this up correctly?

-- import std_logic from the IEEE library
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- this is the entity
entity counter_example is
   port ( 
         counter_out    : buffer unsigned(31 downto 0));
end counter_example;
 
architecture counter_code of counter_example is
signal clock : std_logic := '0';
begin
  process (clock)
  begin
    clock <= not clock after 10 ns; --will give 50MHz clock
    if rising_edge(clock) then
        counter_out <= counter_out + 1;
    end if;
  end process;
end counter_code;

Thanks