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Altera_Forum's avatar
Altera_Forum
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16 years ago

Need help creating a simple 32bit counter

I'm trying to learn VHDL so I thought I'd try converting the "my_first_fpga" example from verilog to VHDL (how complicated can adding one to a number be?), three hours later, lots of googling and sea...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

The edge sensitive condition is missing. See the VHDL templates in Quartus editor for the basic syntax of clock synchronous logic.

Although VHDL is a hardware description language rather than being executed line by line like a C program, you can single step it in a simulator as ModelSim, that is interpreting the VHDL text in this place.