Need help creating a simple 32bit counter

First off, welcome to VHDL.

2nd. There is a reason it is not updating with the variable and its all down to how the language works. You should find that if you swap around the counter + 1 statement and the q <= counter statement (so the Q output is set first) it will work.

This is because variables are updated immediately, whereas signals are not. The code you currently have will work in a simulator, but when you synthesise it, as the variable is used to assing a value to Q, there is no need to store the value in counter between clock cycles (because you have stored the value in Q. Now if you swapped the 2 statements around to this:

if CLK'EVENT AND CLK = '1' then
Q <= counter ;        
counter := counter + 1;           
end if;

The synethsiser notes that counter is not assigned to a register at the end of the process, but you do give the value to Q before you increment it, so it will create one for you to store the value of counter between clocks. Like I said before, either way round will work in simulation, but not in synthesis.

3rdly. As you are new to VHDL please can I ask you to stop using std_logic_unsigned/arith now, and use the IEEE standard instead, which is numeric_std, so you dont get into bad (or old fashioned) habits. You can also use rising_edge(clk) instead of clk'event and clk = '1', as it is slightly safer to use in simulation. The rising_edge function will only trigger when the clk signal changes from '0' or 'L' to '1' or 'H', whereas the latter will trigger whenever the clk signal changes from anything to '1' (so 'X', 'U', '-', '0', 'Z', 'H', 'L').

the numeric_std library offers the signed and unsigned types which you can use in the same file (with the std_logic_unsigned/signed you cannot use both types at the same time). You could also do this counter simply by doing this:

signal counter : unsigned(31 downto 0);
.....
process(clk)
begin
  if rising_edge(clk) then
    counter <= counter + 1;
  end if;
end process;
Q <= std_logic_vector(counter);

Another thing to keep in mind is that port lists only HAVE to be std_logic/vector at the top level, theres nothing to stop you using integers, unsigneds, booleans, fixed point types in the port definition of an entity.