Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Need help creating a simple 32bit counter

I'm trying to learn VHDL so I thought I'd try converting the "my_first_fpga" example from verilog to VHDL (how complicated can adding one to a number be?), three hours later, lots of googling and sea...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Thats the reason why i stay with verilog HDL as VHDL has so much typo for such simple stuff.

module counter_example { CLK, OUT1 Q };

input CLK;

output OUT1;

output [31:0] Q;

always @ ( posedge CLK )

Q <= Q + 1; // or write 32'd1 to avoid warnings due to truncation

always @ ( posedge CLK )

OUT1 <= CLK;

endmodule // thats it

stepping trough like c code, haven't seen that even on our SUN used for ASIC designs with much much more expensiv tools ($$$ per year)