--- Quote Start ---
You should show complete library and signal/variable definition.
Generally, this code is supposed to work. But possibly, you found a way to thwart it.
if CLK'EVENT AND CLK = '1' then
counter := counter + 1;
Q <= counter ;
end if;
--- Quote End ---
Like I said, it thwarts the synthesisor because there it sees no point in registering counter, because it registers Q instead. Because counter never read's back from Q, counter is always assumed to be 0.
The best way to fix it and make it synethsise is swap the 2 statement, or do this instead:
if CLK'EVENT AND CLK = '1' then
counter := Q;
counter := counter + 1;
Q <= counter ;
end if;
Honored Contributor
