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Altera_Forum's avatar
Altera_Forum
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16 years ago

Need help creating a simple 32bit counter

I'm trying to learn VHDL so I thought I'd try converting the "my_first_fpga" example from verilog to VHDL (how complicated can adding one to a number be?), three hours later, lots of googling and sea...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

--- Quote Start ---

You should show complete library and signal/variable definition.

Generally, this code is supposed to work. But possibly, you found a way to thwart it. 

    if CLK'EVENT AND CLK = '1' then
        counter := counter + 1;  
        Q <= counter ;
    end if;

--- Quote End ---

Like I said, it thwarts the synthesisor because there it sees no point in registering counter, because it registers Q instead. Because counter never read's back from Q, counter is always assumed to be 0.

The best way to fix it and make it synethsise is swap the 2 statement, or do this instead: 

    if CLK'EVENT AND CLK = '1' then
  counter := Q;
  counter := counter + 1;  
  Q <= counter ;
  end if;