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Altera_Forum
Honored Contributor
Honored ContributorNeed help creating a simple 32bit counter
I'm trying to learn VHDL so I thought I'd try converting the "my_first_fpga" example from verilog to VHDL (how complicated can adding one to a number be?), three hours later, lots of googling and sea...
Altera_ForumHonored Contributor
Honored ContributorThanks Tricky, that got me up and running :)
Does verilog operate the same way in relation to instruction flow and signal vs variable? Also is there a good source for these idiosyncrasies in the language? In an unrelated question every time I recompile I need to goto Tools -> Simulator Tool -> Generate Functional Simulation Netlist to run a simulation, is there a way to automatically generate the netlist or am I doing something wrong?
