Need help creating a simple 32bit counter

I found the "Start Compilation and Simulation" option in Quartus which saves a few steps, however I thought I'd try setting up a test bench. I installed ModelSim, when I run the simulation and look in wave I can see the clock but counter_out has no value. Did I set this up correctly?

-- import std_logic from the IEEE library
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- this is the entity
entity counter_example is
   port ( 
         counter_out    : buffer unsigned(31 downto 0));
end counter_example;
 
architecture counter_code of counter_example is
signal clock : std_logic := '0';
begin
  process (clock)
  begin
    clock <= not clock after 10 ns; --will give 50MHz clock
    if rising_edge(clock) then
        counter_out <= counter_out + 1;
    end if;
  end process;
end counter_code;