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Altera_Forum's avatar
Altera_Forum
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16 years ago

Need help creating a simple 32bit counter

I'm trying to learn VHDL so I thought I'd try converting the "my_first_fpga" example from verilog to VHDL (how complicated can adding one to a number be?), three hours later, lots of googling and sea...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Thanks, a friend suggested verilog over VHDL, maybe I should listen to him.

Question: The following works 

Q    : buffer  std_logic_vector(31 downto 0));
    if CLK'EVENT AND CLK = '1' then
        Q <= Q + 1 ;
    end if;
But if the counter is stored in a variable and copied to Q on a positive edge it doesn't work.

ie: 

    if CLK'EVENT AND CLK = '1' then
        counter := counter + 1;  
        Q <= counter ;
    end if;

Why doesn't that work?