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Thanks Tricky, that got me up and running :)
Does verilog operate the same way in relation to instruction flow and signal vs variable? Also is there a good source for these idiosyncrasies in the language?
In an unrelated question every time I recompile I need to goto
Tools -> Simulator Tool -> Generate Functional Simulation Netlist
to run a simulation, is there a way to automatically generate the netlist or am I doing something wrong?
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I do not know anything about verilog, though the words blocking and non-blocking assignments has been used before to equate signals and variables in VHDL from time to time.
for the 2nd point you're simulating a post-P&R netlist, which will be slow (but will function as it would on real hardware). In modelsim you can simulate your VHDL text files directly with no synthesis required. You will need to create a testbench to stimulate all of the inputs (like generating a clock) but thats quite straight forward.
To generate a clock in a VHDL testbench you can just use the line:
signal clock : std_logic := '0';
clk <= not clk after 10 ns; --will give 50MHz clock
and then just connect the clock to the clk port on your counter.
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