Forum Discussion
New ContributorJTAG programming not working properly in DE1-SoC Board
Hi,
I have code which instantiates a particular design N no. of times.
When the N>12000 , even though the Quartus tool generates the bitstream, I am not able to configure the FPGA on board(DE1-SoC). Even after programming the new bitstream through JTAG , the board automatically loads the bitstream from serial flash. How and why is this happening? Any suggestions to workaround this?
Thanks & Regards,
Vidya
6 Replies
YuanLi_S_IntelRegular Contributor
Hi Vidya, First of all, may i know which programming file you are programming into the FPGA? SOF or JIC? Secondly, do you power cycle the FPGA after you have programmed the new bitstream? Regards, YL
VGovi4Hello,
I am using .sof file for programming and I am not power cycling after programming. Do you know the reset condition for this board and where it is mentioned?
I am suspecting the board is resetting and then programming the FPGA in default mode which is from the flash.
Regards,
Vidya
- YuanLi_S_IntelHi Vidya, By right it shouldn't be like this. The board will not reset itself unless it is designed so in the FPGA design. You mentioned about N>12000. What about the programming for N<12000? Is it successful? If it so, it might be due to your design problem. Regards, YL
- VGovi4
Hi YL,
For n<12000 the FPGA programming happens as expected. In my design there is no logic of resetting . Infact I am not using HPS part of the device only PL part.
What I observed is for n>12000 the resource utilization goes above 50%. Will that cause a problem?
Regards,
Vidya
- YuanLi_S_IntelHi Vidya, By right it shouldn't have any problem. You can have resources utilization up to 100%, however, you need to ensure that the compilation is successful and timing is clean after compilation. It seems to me that the board is having issue. Regards, YL
- YuanLi_S_IntelHi Vidya, Any update on this? Have you tried with the other board? Regards, YL
