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VGovi4's avatar
VGovi4
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7 years ago

JTAG programming not working properly in DE1-SoC Board

Hi, I have code which instantiates a particular design N no. of times. When the N>12000 , even though the Quartus tool generates the bitstream, I am not able to configure the FPGA on board(DE1-SoC)...
YuanLi_S_Intel's avatar
YuanLi_S_Intel
Icon for Regular Contributor rankRegular Contributor
7 years ago
Hi Vidya, By right it shouldn't be like this. The board will not reset itself unless it is designed so in the FPGA design. You mentioned about N>12000. What about the programming for N<12000? Is it successful? If it so, it might be due to your design problem. Regards, YL
VGovi4's avatar
VGovi4
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7 years ago

Hi YL,

For n<12000 the FPGA programming happens as expected. In my design there is no logic of resetting . Infact I am not using HPS part of the device only PL part.

What I observed is for n>12000 the resource utilization goes above 50%. Will that cause a problem?

Regards,

Vidya