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VGovi4's avatar
VGovi4
Icon for New Contributor rankNew Contributor
7 years ago

JTAG programming not working properly in DE1-SoC Board

Hi, I have code which instantiates a particular design N no. of times. When the N>12000 , even though the Quartus tool generates the bitstream, I am not able to configure the FPGA on board(DE1-SoC)...
YuanLi_S_Intel's avatar
YuanLi_S_Intel
Icon for Regular Contributor rankRegular Contributor
7 years ago
Hi Vidya, By right it shouldn't have any problem. You can have resources utilization up to 100%, however, you need to ensure that the compilation is successful and timing is clean after compilation. It seems to me that the board is having issue. Regards, YL