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MK_ABQ's avatar
MK_ABQ
Icon for Contributor rankContributor
3 years ago
Solved

General question in PLL

Hello,

A general question in PLL. I am currently working with an Intel IP which has an I/O PLL. The PLL will be locked once the input frequency is stable. At the same time, it says the jitter tolerance is about 100 ps. It seems contradictory. If am testing jitter, then the period will keep changing and the PLL is not gonna lock. so how does it work?

Thanks

  • Farabi's avatar
    Farabi
    3 years ago

    Hello,


    In PLL simulation you cannot introduce jitter as the simulation model not include the jitter factors. There is requirement you need to follow for supplying clock source/oscillator to the PLL input, this spec already cover jitter and skew to make sure PLL working as expected in datasheet.


    regards,

    Farabi


6 Replies

  • Mike_Intel's avatar
    Mike_Intel
    Icon for Occasional Contributor rankOccasional Contributor
    3 years ago

    Hello MK_ABQ,


    Thank you for posting in Intel Ethernet Communities.


    For us to further check the issue, please provide the following details.


    1. What is the model of the Intel Ethernet network card that you are using?
    2. Are you designing a board/system with Embedded network card?
    3. Can you tell us more about this test or project that you are doing for us to assist you or route you to the correct team if needed.


    If you have questions, please let us know. In case we do not hear from you, we will make a follow up after 3 workings days. Thank you.


    Best regards,

    Michael L.

    Intel® Customer Support


    • MK_ABQ's avatar
      MK_ABQ
      Icon for Contributor rankContributor
      3 years ago

      Hi Mike,

      I am not using an Ethernet IP. I am using a LVDS IP, and interested specifically to understand jitter/PLL behavior. Should I post this question in a different group?

      Thanks

  • Mike_Intel's avatar
    Mike_Intel
    Icon for Occasional Contributor rankOccasional Contributor
    3 years ago

    Hello MK_ABQ,


    Thank you for the update. Since you are inquiring about an FPGA product. I will route your case and thread to the correct group.


    Please wait for their reply within 1 to 2 business days.


    Thank you and stay safe.


    Best regards,

    Michael L.

    Intel® Customer Support


  • AqidAyman_Altera's avatar
    AqidAyman_Altera
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hello,


    Thank you for reaching out to Intel FPGA Community.


    Could you share which device are you using?


    Regards,

    Aqid Ayman


    • MK_ABQ's avatar
      MK_ABQ
      Icon for Contributor rankContributor
      3 years ago

      Hi,

      I am using Arria 10 FPGA. How do I introduce jitter in simulation ?

  • Farabi's avatar
    Farabi
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hello,


    In PLL simulation you cannot introduce jitter as the simulation model not include the jitter factors. There is requirement you need to follow for supplying clock source/oscillator to the PLL input, this spec already cover jitter and skew to make sure PLL working as expected in datasheet.


    regards,

    Farabi