Forum Discussion
MK_ABQ
Contributor
ContributorGeneral question in PLL
Hello,
A general question in PLL. I am currently working with an Intel IP which has an I/O PLL. The PLL will be locked once the input frequency is stable. At the same time, it says the jitter toler...
Hello,
In PLL simulation you cannot introduce jitter as the simulation model not include the jitter factors. There is requirement you need to follow for supplying clock source/oscillator to the PLL input, this spec already cover jitter and skew to make sure PLL working as expected in datasheet.
regards,
Farabi
Mike_Intel
Occasional Contributor
Occasional ContributorHello MK_ABQ,
Thank you for the update. Since you are inquiring about an FPGA product. I will route your case and thread to the correct group.
Please wait for their reply within 1 to 2 business days.
Thank you and stay safe.
Best regards,
Michael L.
Intel® Customer Support
