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MK_ABQ's avatar
MK_ABQ
Icon for Contributor rankContributor
3 years ago
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General question in PLL

Hello, A general question in PLL. I am currently working with an Intel IP which has an I/O PLL. The PLL will be locked once the input frequency is stable. At the same time, it says the jitter toler...
  • Farabi's avatar
    Farabi
    3 years ago

    Hello,


    In PLL simulation you cannot introduce jitter as the simulation model not include the jitter factors. There is requirement you need to follow for supplying clock source/oscillator to the PLL input, this spec already cover jitter and skew to make sure PLL working as expected in datasheet.


    regards,

    Farabi


Farabi's avatar
Farabi
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hello,


In PLL simulation you cannot introduce jitter as the simulation model not include the jitter factors. There is requirement you need to follow for supplying clock source/oscillator to the PLL input, this spec already cover jitter and skew to make sure PLL working as expected in datasheet.


regards,

Farabi