Forum Discussion
MK_ABQ
Contributor
ContributorGeneral question in PLL
Hello,
A general question in PLL. I am currently working with an Intel IP which has an I/O PLL. The PLL will be locked once the input frequency is stable. At the same time, it says the jitter toler...
Hello,
In PLL simulation you cannot introduce jitter as the simulation model not include the jitter factors. There is requirement you need to follow for supplying clock source/oscillator to the PLL input, this spec already cover jitter and skew to make sure PLL working as expected in datasheet.
regards,
Farabi
AqidAyman_Altera
Regular Contributor
Regular ContributorHello,
Thank you for reaching out to Intel FPGA Community.
Could you share which device are you using?
Regards,
Aqid Ayman
MK_ABQHi,
I am using Arria 10 FPGA. How do I introduce jitter in simulation ?
