Ethernet with DSP Dev. Kit Cyclone III (no NIOS)

Thanks for your responses.

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I'd look at the udp offload (http://www.nioswiki.com/exampledesigns/nios2udpoffloadexample) example on the Wiki. That should give you the performance you desire.

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Hopefully it will work with Quartus II 8.0, too...

I will try both but I can't do this by now because my development kit / board is not yet delivered.

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You can use C-2-H feature for converting your Nios C code into hardware. Using this all your c code convert into hardware block by altera tools and surly you will get the speed. But condition is that your c code is without any altera API ( like IORD, IOWR etc... ).

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"The C2H Compiler improves the performance of Nios II programs by implementing specific C functions as hardware accelerators. the c2h compiler is not designed to create arbitrary hardware systems from c code. Rather, the C2H Compiler is a tool for generating a hardware accelerator module, functionally identical to the original C function, that offloads and enhances the performance of the Nios II processor."

"The C2H Compiler is not designed to build all types of FPGA systems. It is designed specifically to augment the performance of programs that run on the Nios II processor; it does not replace the processor."

(source: http://www.altera.com/literature/ug/ug_nios2_c2h_compiler.pdf)

-> So it is not exactly what I am looking for. But OK, finally there are two possibilities and both of them have some disadvantages:

• I could use TripleSpeedEthernet with avalon opencores 10/100 ethernet mac (http://www.niosforum.com/pages/project_details.php?p_id=115&t_id=18) and code at least the ARP and UDP/IP protocols in hardware.

• An alternative would be to use the NIOS processor, but the NIOS processor is slower than a FPGA. With the C2H Compiler I can improve the performance of a NIOS C-program, but I don't want a NIOS C-program. I want to use only the FPGA without NIOS.

So it seem's difficult...

I don't think that there is a freeware ip-core for FPGAs which makes ethernet/ip extremely simple. I think I'll have to use the nios, otherwise it would take a half year... I don't have that much time...

The Nios is the easiest way if you don't want to spend too much time on the project.

If you need performance, the offload example given by slaker is a good way to go: you use a CPU for all the protocols that are better handled in software (ARP, TCP...) and use hardware only for specific high-speed UDP ports.

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The Nios is the easiest way if you don't want to spend too much time on the project.

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On the one hand, I got several months to get it working but on the other hand I am still a beginner...

I got another question:

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Also included is a complete MAC driver to be used in conjunction with Altera's implementation of the InterNiche TCP/IP Stack. The driver and MAC have been tested with both the UCOSII and Superloop implementations of the stack. you should be able to drop it into your system and be able to run altera's simplesocket server example without problems. You may need to do a little work to support your PHY (explained in the enclosed MSWORD document).

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I downloaded this and put it in Quartus but I couldn't understand how to use this, even not when reading the included Guide (the DOC-File). But if it says that I should be able to run the SimpleSocket Server example, so it is not true that I need to code ARP/TCP/... by myself, because I think that this InterNiche TCP/IP Stack is doing this for me.

Where can I read how to use the avalon opencores 10/100 ethernet mac and who can give me an example design with it and Cyclone III Board?

Yes, if you use the Interniche stack all the protocols will be handled automatically and you can just use the standard socket API.

As for the example design, I don't think they made any for the DSP kit that includes the Ethernet interface. You can have a look at the nios ii 3c120 design example (http://www.nioswiki.com/exampledesigns/niosii3c120designexample) on the Nios Wiki.

For the software side you can create a Simple Sockets Server project directly from the IDE.

OK, so let me resume what I have understood until now (please correct me if I am wrong):

If we look in wikipedia in the article ethernet (http://en.wikipedia.org/wiki/ethernet) we can see how the different layers are called:

• Application Layer

• Transport Layer

• Internet Layer

• Link Layer

For the link layer I can use the IP-core called "Triple Speed Ethernet" in Quartus. But the problem is, that the layers above the Link Layer must be handled too and there are no IP-cores for that in FPGA/Hardware. I could code this by myself but this would take much time, wouldn't it?

So I use software (the NIOS II processor) to do that. There I can use for example the avalon opencores 10/100 ethernet mac (http://www.niosforum.com/pages/project_details.php?p_id=115&t_id=18) or in this case nios 2 udp offload example (http://www.nioswiki.com/exampledesigns/nios2udpoffloadexample) (because very high speed is needed). I can accelerate the software in the processor by the c-to-hardware-compiler from NIOS to get even more speed.

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The example also implements hardware components capable of creating UDP packets and multiplexing them together with Nios II subsystem traffic for transmission out the Altera TSE MAC interface.

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So I can also send data from my board to another ethernet-device (for example a pc) with high speed.

When you are communicating with the PC, you are sending IP packets, either TCP or UDP. Those protocols are in the Network and Transport layers.

To transmit IP packets from one system to another, you need a link that is on the Physical layer. Ethernet is the most popular today.

To implement an Ethernet link, you need 3 parts:

• the PHY chip, that contains the analog front end. It is usually outside of the FPGA on the PCB.

• the MAC, that implements the protocol. It can be either outside the FPGA or inside, as an IP. On the 3C120 kit you need to have it in the FPGA

• the driver, that takes an IP packet and adds the Ethernet header, to build an Ethernet frame ready for the MAC to transmit, or in the other direction that decodes an incoming frame to recover the IP packet.

In your case the PHY chip is already on the board. It is a Marvell 88E1111 chip. For the MAC you have two choices:

• Triple Speed Ethernet, provided by Altera

• Avalon Opencores Ethernet MAC, opensource

At last for the driver, it is easier to use a CPU. With the Nios drivers for both MACs can be found for several operating systems, including uC OS which is directly supported in the IDE.

It is the easiest solution, but the CPU will limit the actual bandwidth that you can expect from the system. You will need some optimisations to go over a few tens of Mbits/s.

If you need much more speed, you need to generate the Ethernet frames in hardware. This is what is demonstrated in the offload example. This hardware part replaces (or is placed in parallel of) the software driver, but you still need a MAC and a PHY. If you want to go in that direction, I recommend to use the Altera MAC. It is easier to interface directly with hardware, through the Avalon stream interfaces. The Opencores solution will be harder to connect to hardware due to its embedded DMA controller.

If you choose the hardware way, remember that you need to fill in the complete packet headers, including Ethernet, IP and UPD. Once you've filled in everything, you can just send the frame to the MAC and it will be transmitted.

Thanks for your response, that helped a lot!

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If you choose the hardware way, remember that you need to fill in the complete packet headers, including Ethernet, IP and UPD.

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OK.

I am sorry if I am changing the subject/topic so abruptly, but my next question is:

Do you think it would be a more simple and faster solution to use USB instead for communicating with the PC?

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The downsides to USB are that it has limited connectivity (length, point-to-point) and you have to write everything pretty much yourself. You don't get to take advantage of the existing software and hardware that are built around TCP/IP. Ethernet is nice because you don't have to write any of the low-level stuff.

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So here we can compare now: What is more difficult: Generating the Ethernet frames in hardware (and fill in all these headers) or using USB and writing everything pretty much myself?

To generate the Ethernet frames in hardware, you need to know the PC's MAC address (that is usually found from it's IP using the ARP protocol) and compute the IP and UDP checksums.

For the USB communication, the USB part of the board isn't documented, and it doesn't seem easy. There is another thread on that subject in this forum. An alternative would be to use the embedded USB blaster in JTAG mode, and use the system console tools on the PC to directly access the Nios' memory and read the data in there. Unfortunately I'm not sure the performance will be very high...

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...directly access the nios' memory

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I think the size of the Nios' memory is about 4 MBit. So I guess it's not the same as the ddr2-sdram on the Board...

For my project, I think I am going to use Ethernet (with NIOS). My VHDL-Hardware will fill the DDR2-SDRAM with Data (received from ADC). Then the NIOS should read the DDR2-SDRAM and send the Data via Ethernet to the PC. I will take care of the speed of Ethernet later, at first I am glad if it works at all...

In this case, my hardware and software are independent in a way. Could there be problems when the FPGA and the NIOS both access the DDR2-SDRAM?

Thank you, Daixiwen! :)