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You can use C-2-H feature for converting your Nios C code into hardware. Using this all your c code convert into hardware block by altera tools and surly you will get the speed. But condition is that your c code is without any altera API ( like IORD, IOWR etc... ).
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"The C2H Compiler improves the performance of Nios II programs by implementing specific C functions as hardware accelerators.
the c2h compiler is not designed to create arbitrary hardware systems from c code. Rather, the C2H Compiler is a tool for generating a hardware accelerator module, functionally identical to the original C function, that offloads and enhances the performance of the Nios II processor."
"The C2H Compiler is not designed to build all types of FPGA systems. It is designed specifically to
augment the performance of programs that run on the Nios II processor;
it does not replace the processor."
(source:
http://www.altera.com/literature/ug/ug_nios2_c2h_compiler.pdf)
-> So it is not exactly what I am looking for. But OK, finally there are two possibilities and both of them have some disadvantages:
- I could use TripleSpeedEthernet with avalon opencores 10/100 ethernet mac (http://www.niosforum.com/pages/project_details.php?p_id=115&t_id=18) and code at least the ARP and UDP/IP protocols in hardware.
- An alternative would be to use the NIOS processor, but the NIOS processor is slower than a FPGA. With the C2H Compiler I can improve the performance of a NIOS C-program, but I don't want a NIOS C-program. I want to use only the FPGA without NIOS.
So it seem's difficult...
I don't think that there is a freeware ip-core for FPGAs which makes ethernet/ip extremely simple. I think I'll have to use the
nios, otherwise it would take a half year... I don't have that much time...
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