OK, so let me resume what I have understood until now (please correct me if I am wrong):
If we look in wikipedia in the article ethernet (
http://en.wikipedia.org/wiki/ethernet) we can see how the different layers are called:
- Application Layer
- Transport Layer
- Internet Layer
- Link Layer
For the
link layer I can use the IP-core called "Triple Speed Ethernet" in Quartus. But the problem is, that the layers above the Link Layer must be handled too and there are no IP-cores for that in FPGA/Hardware. I could code this by myself but this would take much time, wouldn't it?
So I use software (the NIOS II processor) to do that. There I can use for example the avalon opencores 10/100 ethernet mac (
http://www.niosforum.com/pages/project_details.php?p_id=115&t_id=18) or in this case nios 2 udp offload example (
http://www.nioswiki.com/exampledesigns/nios2udpoffloadexample) (because very high speed is needed). I can accelerate the software in the processor by the c-to-hardware-compiler from NIOS to get even more speed.
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The example also implements hardware components capable of creating UDP packets and multiplexing them together with Nios II subsystem traffic for transmission out the Altera TSE MAC interface.
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So I can also send data from my board to another ethernet-device (for example a pc) with high speed.
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