Cyclone V - Differential Pair Pin Assignment 1.5V PCML fitter error

Okay, Quartus Prime Lite16.1 but I can change that if needed.

I don't see a .qar file, but here is the project folder contents

Here is the .qsf file:

# Quartus Prime
# Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
# Date created = 11:58:04 July 18, 2022
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# CPL_Loopback_1_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #

set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name DEVICE 5CGXFC5C6F27C7
set_global_assignment -name TOP_LEVEL_ENTITY C5G_HSMC_XCVR_LOOPBACK_TEST
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:58:04 JULY 18, 2022"
set_global_assignment -name LAST_QUARTUS_VERSION "16.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
set_global_assignment -name VERILOG_FILE V/C5G_HSMC_XCVR_LOOPBACK_TEST.v
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_location_assignment PIN_R20 -to CLOCK_50_B5B
set_location_assignment PIN_N20 -to CLOCK_50_B6A
set_location_assignment PIN_H12 -to CLOCK_50_B7A
set_location_assignment PIN_M10 -to CLOCK_50_B8A
set_location_assignment PIN_U12 -to CLOCK_125_p
set_location_assignment PIN_AB24 -to CPU_RESET_n
set_instance_assignment -name IO_STANDARD LVDS -to CLOCK_125_p
set_location_assignment PIN_V12 -to "CLOCK_125_p(n)"
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50_B5B
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50_B6A
set_instance_assignment -name IO_STANDARD "2.5 V" -to CLOCK_50_B7A
set_instance_assignment -name IO_STANDARD "2.5 V" -to CLOCK_50_B8A
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CPU_RESET_n
set_location_assignment PIN_V19 -to HEX0[0]
set_location_assignment PIN_V18 -to HEX0[1]
set_location_assignment PIN_V17 -to HEX0[2]
set_location_assignment PIN_W18 -to HEX0[3]
set_location_assignment PIN_Y20 -to HEX0[4]
set_location_assignment PIN_Y19 -to HEX0[5]
set_location_assignment PIN_Y18 -to HEX0[6]
set_location_assignment PIN_AA18 -to HEX1[0]
set_location_assignment PIN_AD26 -to HEX1[1]
set_location_assignment PIN_AB19 -to HEX1[2]
set_location_assignment PIN_AE26 -to HEX1[3]
set_location_assignment PIN_AE25 -to HEX1[4]
set_location_assignment PIN_AC19 -to HEX1[5]
set_location_assignment PIN_AF24 -to HEX1[6]
set_instance_assignment -name IO_STANDARD "1.2 V" -to HEX0[0]
set_instance_assignment -name IO_STANDARD "1.2 V" -to HEX0[1]
set_instance_assignment -name IO_STANDARD "1.2 V" -to HEX0[2]
set_instance_assignment -name IO_STANDARD "1.2 V" -to HEX0[3]
set_instance_assignment -name IO_STANDARD "1.2 V" -to HEX0[4]
set_instance_assignment -name IO_STANDARD "1.2 V" -to HEX0[5]
set_instance_assignment -name IO_STANDARD "1.2 V" -to HEX0[6]
set_instance_assignment -name IO_STANDARD "1.2 V" -to HEX1[0]
set_instance_assignment -name IO_STANDARD "1.2 V" -to HEX1[1]
set_instance_assignment -name IO_STANDARD "1.2 V" -to HEX1[2]
set_instance_assignment -name IO_STANDARD "1.2 V" -to HEX1[3]
set_instance_assignment -name IO_STANDARD "1.2 V" -to HEX1[4]
set_instance_assignment -name IO_STANDARD "1.2 V" -to HEX1[5]
set_instance_assignment -name IO_STANDARD "1.2 V" -to HEX1[6]
set_location_assignment PIN_AD2 -to HSMC_GXB_RX_p[0]
set_location_assignment PIN_AE4 -to HSMC_GXB_TX_p[0]
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_RX_p[0]
set_location_assignment PIN_AD1 -to "HSMC_GXB_RX_p[0](n)"
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_TX_p[0]
set_location_assignment PIN_AE3 -to "HSMC_GXB_TX_p[0](n)"
set_location_assignment PIN_H9 -to LEDG[7]
set_location_assignment PIN_H8 -to LEDG[6]
set_location_assignment PIN_B6 -to LEDG[5]
set_location_assignment PIN_A5 -to LEDG[4]
set_location_assignment PIN_E9 -to LEDG[3]
set_location_assignment PIN_D8 -to LEDG[2]
set_location_assignment PIN_K6 -to LEDG[1]
set_location_assignment PIN_L7 -to LEDG[0]
set_location_assignment PIN_J10 -to LEDR[9]
set_location_assignment PIN_H7 -to LEDR[8]
set_location_assignment PIN_K8 -to LEDR[7]
set_location_assignment PIN_K10 -to LEDR[6]
set_location_assignment PIN_J7 -to LEDR[5]
set_location_assignment PIN_J8 -to LEDR[4]
set_location_assignment PIN_G7 -to LEDR[3]
set_location_assignment PIN_G6 -to LEDR[2]
set_location_assignment PIN_F6 -to LEDR[1]
set_location_assignment PIN_F7 -to LEDR[0]
set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[7]
set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[6]
set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[5]
set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[4]
set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[3]
set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[2]
set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[1]
set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[0]
set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[9]
set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[8]
set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[7]
set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[6]
set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[5]
set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[4]
set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[3]
set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[2]
set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[1]
set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[0]
set_location_assignment PIN_C20 -to HSMC_EQBypass_1
set_location_assignment PIN_B19 -to HSMC_EQBypass_2
set_location_assignment PIN_B12 -to HSMC_SDI_CLK_Sel
set_location_assignment PIN_B10 -to HSMC_SDI_Rate_Sel_1
set_location_assignment PIN_A11 -to HSMC_SDI_Rate_Sel_2
set_location_assignment PIN_A13 -to HSMC_SDI_XTAL_Sel
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_EQBypass_1
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_EQBypass_2
set_location_assignment PIN_A17 -to HSMC_CLKOUT_p[2]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLKOUT_p[2]
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name SMART_RECOMPILE ON
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_SDI_XTAL_Sel
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_SDI_Rate_Sel_2
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_SDI_Rate_Sel_1
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_SDI_CLK_Sel
set_global_assignment -name QIP_FILE SDI_v16_t.qip
set_global_assignment -name QIP_FILE PLL_XCVR.qip
set_global_assignment -name SIP_FILE PLL_XCVR.sip
set_global_assignment -name IP_SEARCH_PATHS "c:\\projects\\chilipepperlabs\\dev boards\\cyclone 5 gx starter kit\\cpl_hdl_16_1\\sdi-library;c:\\projects\\chilipepperlabs\\dev boards\\cyclone 5 gx starter kit\\cpl_hdl_16_1"
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

Hi Terra,

I cannot use google drive in our PC's.

You should use only SDI II.

SDI v16.1 is very old.

Here, You need to do "Generate transceiver only". Protocol blocks depends on your design requirement and I don't think you need it now.

In the project options, you can archive the project and send it to me.

Thank you

Kshitij Goel

I've switched to Quartus Prime 21.1 and added the IP Core for "SDI II Intel FPGA IP"

I selected the options for Transceiver Only, Bidirectional, HD-SDI, and 74.25MHz

Then I added a PLL to provide the clock, but it doesn't seem to compile with the PLL.

Thank you for your help. I created the Archive .qar file and attached it.

Still trying to instantiate the "SDI II Intel FPGA IP" core. I tried creating another PLL. This time with the "Fractional" option to output the 74.25MHz signal.

I am still getting a Fitter Error.

Info (184020): Starting Fitter periphery placement operations
Error (14996): The Fitter failed to find a legal placement for all periphery components
Info (14987): The following components had the most difficulty being legally placed:
Info (175029): fractional PLL intel_fract_PLL_50:XCVR_PLL_2|intel_fract_PLL_50_0002:intel_fract_pll_50_inst|altera_pll:altera_pll_i|general[0].gpll~FRACTIONAL_PLL (100%)
Error (14986): After placing as many components as possible, the following errors remain:
Error (175001): The Fitter cannot place 1 global or regional clock driver, which is within PLL Intel FPGA IP intel_fract_PLL_50.
Info (14596): Information about the failing component(s):
Info (175028): The global or regional clock driver name(s): intel_fract_PLL_50:XCVR_PLL_2|intel_fract_PLL_50_0002:intel_fract_pll_50_inst|altera_pll:altera_pll_i|outclk_wire[0]~CLKENA0
Error (16234): No legal location could be found out of 46 considered location(s). Reasons why each location could not be used are summarized below:
Error (15123): The following global or regional clock driver locations cannot route to all the required HSSI TX PLD PCS Interfaces
Info (175027): Destination: HSSI TX PLD PCS Interface SDI_XCVR:SDI_ii_Bidirectional1|SDI_XCVR_0002:sdi_xcvr_inst|altera_xcvr_native_av:u_phy|av_xcvr_native:gen_native_inst.av_xcvr_native_insts[0].gen_bonded_group_native.av_xcvr_native_inst|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_tx_pld_pcs_interface_rbc:inst_av_hssi_tx_pld_pcs_interface|wys
Info (175029): 16 locations affected
Info (175029): CLKCTRL_R82
Info (175029): CLKCTRL_R83
Info (175029): CLKCTRL_R84
Info (175029): CLKCTRL_R85
Info (175029): CLKCTRL_R86
Info (175029): CLKCTRL_R87
Info (175029): CLKCTRL_R10
Info (175029): CLKCTRL_R11
Info (175029): CLKCTRL_R12
Info (175029): CLKCTRL_R13
Info (175029): CLKCTRL_R14
Info (175029): CLKCTRL_R15
Info (175029): and 4 more locations not displayed
Info (175013): The global or regional clock driver is constrained to the region (0, to (28, 61) due to related logic
Info (175015): The I/O pad CLOCK_50_B7A is constrained to the location PIN_H12 due to: User Location Constraints (PIN_H12)
Info (14709): The constrained I/O pad is contained within a pin, which drives a fractional PLL, which drives a PLL output counter, which drives this global or regional clock driver
Error (175007): Could not find uncongested path between source PLL output counter and the global or regional clock driver
Info (175026): Source: PLL output counter intel_fract_PLL_50:XCVR_PLL_2|intel_fract_PLL_50_0002:intel_fract_pll_50_inst|altera_pll:altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER
Info (175013): The PLL output counter is constrained to the region (0, 17) to (0, 33) due to related logic
Info (175015): The I/O pad CLOCK_50_B7A is constrained to the location PIN_H12 due to: User Location Constraints (PIN_H12)
Info (14709): The constrained I/O pad is contained within a pin, which drives a fractional PLL, which drives this PLL output counter
Info (175021): The PLL output counter was placed in location PLLOUTPUTCOUNTER_X0_Y29_N1
Error (175022): The global or regional clock driver could not be placed in any location to satisfy its connectivity requirements
Info (175029): 30 locations affected
Info (175029): CLKCTRL_G0
Info (175029): CLKCTRL_G1
Info (175029): CLKCTRL_G2
Info (175029): CLKCTRL_G3
Info (175029): CLKCTRL_R64
Info (175029): CLKCTRL_R65
Info (175029): CLKCTRL_R66
Info (175029): CLKCTRL_R67
Info (175029): CLKCTRL_R68
Info (175029): CLKCTRL_R69
Info (175029): CLKCTRL_R40
Info (175029): CLKCTRL_R41
Info (175029): and 18 more locations not displayed
Info (184021): Fitter periphery placement operations ending: elapsed time is 00:00:00

One idea I have about this error message is that the Clock pin I'm using for the PLL (CLOCK_50_B7A on Bank 7) is on a separate bank from the Tx & Rx pins (which are on bank GXB_L0). If that is the case, then I only have REFCLK_p0 to work with as the input to the PLL since it is on the same bank as the Rx & Tx pins I am trying to connect together. Does that sound about right?

OK, using the REFCLK_p0 is one step further. I can compile it now when I replace the xcvr_refclk input from the PLL to the REFCLK_p0 pin. I believe on the C5G starter kit board the REFCLK_p0 pin is fixed at 125MHz. The project however still does not work as intended. The signal going into the RX pin is not coming out the TX pin. Here is the newer updated QAR attached.

Here is a picture of the RTL viewer:

I had hooked the "Tx_dataout_valid" signal right back into the "tx_datain_valid" signal but I'm not sure if that is right.

Please help.

Hi,

Few question for you.

Q1. What are you feeding to TX as an input, there must be some initial value?

Q2. If there is how are you feeding it?

Even though you feed some constant value to the transmit, there is higher probability you will see the bit shift at the receiver. You need to reconstruct the word or design a word aligner in the FPGA fabric.

On top of everything, you should not try in this way of looping back.

Thank you

Kshitij Goel

I am feeding Rx into Tx, so Tx initial value will be the same as Rx.

I have tried to loop all the Rx wires into the Tx inputs.

Here is where I am feeding the Tx:

.tx_datain ( SDI_Databus20 ), // input wire [19:0] tx_datain.export
.tx_datain_valid ( Tx_dataout_valid ),// input wire generate a tx_datain_valid pulse every other clock cycle of the tx_pclk domain
.tx_dataout_valid ( Tx_dataout_valid ),// output wire tx_dataout_valid.export
.tx_pclk ( FRACT_74_25MHZ ), // input wire tx_pclk.clk
.tx_coreclk_hd ( FRACT_74_25MHZ ), // input wire This clock source must be always stable and can be shared with xcvr_refclk
.rx_coreclk_is_ntsc_paln ( 1'b0 ), // input wire 0 = PAL rate (when rx_coreclk = 297 / 148.5 MHz or rx_coreclk_hd = 74.25 MHz)
.rx_clkout_is_ntsc_paln ( ), // output wire rx_clkout_is_ntsc_paln.export
.rx_trs_in ( ), // input wire [0:0] indicate to the PHY management block that the receiver protocol block detected a valid TRS.
.rx_trs_loose_lock_in ( ), // input wire [0:0] This signal must be driven by rx_trs_loose_lock_out of the receiver protocol block.
.rx_dataout ( SDI_Databus20 ), // output wire [19:0] rx_dataout.export
.rx_dataout_valid ( ), // output wire rx_dataout_valid.export
.rx_clkout ( ), // output wire rx_clkout.clk
.rx_rst_proto_out ( ), // output wire rx_rst_proto_out.export
.rx_rst ( ~reset_n ), // input wire rx_rst.reset
.rx_coreclk_hd ( FRACT_74_25MHZ ), // input wire rx_coreclk_hd.clk
.xcvr_refclk ( REFCLK_p0 ), // input wire << Must be on the Same BANK as the sdi_tx & sdi_rx FPGA pins.
.sdi_tx ( HSMC_GXB_TX_p ), // output wire sdi_tx.export
.tx_pll_locked ( ), // output wire tx_pll_locked.export
.tx_clkout ( ), // output wire tx_clkout.clk
.sdi_rx ( HSMC_GXB_RX_p ), // input wire sdi_rx.export

"On top of everything, you should not try in this way of looping back." -K**bleep**ij Goel

My question from the beginning, has been: What is the best way to connect the HSMC_GXB_RX pin to the HSMC_GXB_TX pin together inside the FPGA?

Please suggest what is the best way to try this way of looping back.