Cyclone V - Differential Pair Pin Assignment 1.5V PCML fitter error

Still trying to instantiate the "SDI II Intel FPGA IP" core. I tried creating another PLL. This time with the "Fractional" option to output the 74.25MHz signal.

I am still getting a Fitter Error.

Info (184020): Starting Fitter periphery placement operations
Error (14996): The Fitter failed to find a legal placement for all periphery components
Info (14987): The following components had the most difficulty being legally placed:
Info (175029): fractional PLL intel_fract_PLL_50:XCVR_PLL_2|intel_fract_PLL_50_0002:intel_fract_pll_50_inst|altera_pll:altera_pll_i|general[0].gpll~FRACTIONAL_PLL (100%)
Error (14986): After placing as many components as possible, the following errors remain:
Error (175001): The Fitter cannot place 1 global or regional clock driver, which is within PLL Intel FPGA IP intel_fract_PLL_50.
Info (14596): Information about the failing component(s):
Info (175028): The global or regional clock driver name(s): intel_fract_PLL_50:XCVR_PLL_2|intel_fract_PLL_50_0002:intel_fract_pll_50_inst|altera_pll:altera_pll_i|outclk_wire[0]~CLKENA0
Error (16234): No legal location could be found out of 46 considered location(s). Reasons why each location could not be used are summarized below:
Error (15123): The following global or regional clock driver locations cannot route to all the required HSSI TX PLD PCS Interfaces
Info (175027): Destination: HSSI TX PLD PCS Interface SDI_XCVR:SDI_ii_Bidirectional1|SDI_XCVR_0002:sdi_xcvr_inst|altera_xcvr_native_av:u_phy|av_xcvr_native:gen_native_inst.av_xcvr_native_insts[0].gen_bonded_group_native.av_xcvr_native_inst|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_tx_pld_pcs_interface_rbc:inst_av_hssi_tx_pld_pcs_interface|wys
Info (175029): 16 locations affected
Info (175029): CLKCTRL_R82
Info (175029): CLKCTRL_R83
Info (175029): CLKCTRL_R84
Info (175029): CLKCTRL_R85
Info (175029): CLKCTRL_R86
Info (175029): CLKCTRL_R87
Info (175029): CLKCTRL_R10
Info (175029): CLKCTRL_R11
Info (175029): CLKCTRL_R12
Info (175029): CLKCTRL_R13
Info (175029): CLKCTRL_R14
Info (175029): CLKCTRL_R15
Info (175029): and 4 more locations not displayed
Info (175013): The global or regional clock driver is constrained to the region (0, to (28, 61) due to related logic
Info (175015): The I/O pad CLOCK_50_B7A is constrained to the location PIN_H12 due to: User Location Constraints (PIN_H12)
Info (14709): The constrained I/O pad is contained within a pin, which drives a fractional PLL, which drives a PLL output counter, which drives this global or regional clock driver
Error (175007): Could not find uncongested path between source PLL output counter and the global or regional clock driver
Info (175026): Source: PLL output counter intel_fract_PLL_50:XCVR_PLL_2|intel_fract_PLL_50_0002:intel_fract_pll_50_inst|altera_pll:altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER
Info (175013): The PLL output counter is constrained to the region (0, 17) to (0, 33) due to related logic
Info (175015): The I/O pad CLOCK_50_B7A is constrained to the location PIN_H12 due to: User Location Constraints (PIN_H12)
Info (14709): The constrained I/O pad is contained within a pin, which drives a fractional PLL, which drives this PLL output counter
Info (175021): The PLL output counter was placed in location PLLOUTPUTCOUNTER_X0_Y29_N1
Error (175022): The global or regional clock driver could not be placed in any location to satisfy its connectivity requirements
Info (175029): 30 locations affected
Info (175029): CLKCTRL_G0
Info (175029): CLKCTRL_G1
Info (175029): CLKCTRL_G2
Info (175029): CLKCTRL_G3
Info (175029): CLKCTRL_R64
Info (175029): CLKCTRL_R65
Info (175029): CLKCTRL_R66
Info (175029): CLKCTRL_R67
Info (175029): CLKCTRL_R68
Info (175029): CLKCTRL_R69
Info (175029): CLKCTRL_R40
Info (175029): CLKCTRL_R41
Info (175029): and 18 more locations not displayed
Info (184021): Fitter periphery placement operations ending: elapsed time is 00:00:00