New ContributorHi Terra,
I have told you earlier, you cannot directly connect, Please design custom logic to reconstruct the word. First correct your design then try to compile.
Thank you
Kshitij Goel
New Contributor
I am feeding Rx into Tx, so Tx initial value will be the same as Rx.
I have tried to loop all the Rx wires into the Tx inputs.
Here is where I am feeding the Tx:
.tx_datain ( SDI_Databus20 ), // input wire [19:0] tx_datain.export
.tx_datain_valid ( Tx_dataout_valid ),// input wire generate a tx_datain_valid pulse every other clock cycle of the tx_pclk domain
.tx_dataout_valid ( Tx_dataout_valid ),// output wire tx_dataout_valid.export
.tx_pclk ( FRACT_74_25MHZ ), // input wire tx_pclk.clk
.tx_coreclk_hd ( FRACT_74_25MHZ ), // input wire This clock source must be always stable and can be shared with xcvr_refclk
.rx_coreclk_is_ntsc_paln ( 1'b0 ), // input wire 0 = PAL rate (when rx_coreclk = 297 / 148.5 MHz or rx_coreclk_hd = 74.25 MHz)
.rx_clkout_is_ntsc_paln ( ), // output wire rx_clkout_is_ntsc_paln.export
.rx_trs_in ( ), // input wire [0:0] indicate to the PHY management block that the receiver protocol block detected a valid TRS.
.rx_trs_loose_lock_in ( ), // input wire [0:0] This signal must be driven by rx_trs_loose_lock_out of the receiver protocol block.
.rx_dataout ( SDI_Databus20 ), // output wire [19:0] rx_dataout.export
.rx_dataout_valid ( ), // output wire rx_dataout_valid.export
.rx_clkout ( ), // output wire rx_clkout.clk
.rx_rst_proto_out ( ), // output wire rx_rst_proto_out.export
.rx_rst ( ~reset_n ), // input wire rx_rst.reset
.rx_coreclk_hd ( FRACT_74_25MHZ ), // input wire rx_coreclk_hd.clk
.xcvr_refclk ( REFCLK_p0 ), // input wire << Must be on the Same BANK as the sdi_tx & sdi_rx FPGA pins.
.sdi_tx ( HSMC_GXB_TX_p ), // output wire sdi_tx.export
.tx_pll_locked ( ), // output wire tx_pll_locked.export
.tx_clkout ( ), // output wire tx_clkout.clk
.sdi_rx ( HSMC_GXB_RX_p ), // input wire sdi_rx.export
