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TerraX
New Contributor
3 years agoOK, using the REFCLK_p0 is one step further. I can compile it now when I replace the xcvr_refclk input from the PLL to the REFCLK_p0 pin. I believe on the C5G starter kit board the REFCLK_p0 pin is fixed at 125MHz. The project however still does not work as intended. The signal going into the RX pin is not coming out the TX pin. Here is the newer updated QAR attached.
Here is a picture of the RTL viewer:
I had hooked the "Tx_dataout_valid" signal right back into the "tx_datain_valid" signal but I'm not sure if that is right.
Please help.