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TerraX's avatar
TerraX
Icon for New Contributor rankNew Contributor
3 years ago
Solved

Cyclone V - Differential Pair Pin Assignment 1.5V PCML fitter error

When creating a new Quartus project similar to a demo example, I am trying to place XCVR pins in a blank project and getting an error from the 1.5V PMCL differential pins (HSMC_GXB_RX_p0 and HSMC_GXB...
  • Kshitij_Intel's avatar
    Kshitij_Intel
    3 years ago

    Hi Terra,


    I have told you earlier, you cannot directly connect, Please design custom logic to reconstruct the word. First correct your design then try to compile.


    Thank you

    Kshitij Goel


TerraX's avatar
TerraX
Icon for New Contributor rankNew Contributor
3 years ago

I've switched to Quartus Prime 21.1 and added the IP Core for "SDI II Intel FPGA IP"

I selected the options for Transceiver Only, Bidirectional, HD-SDI, and 74.25MHz

Then I added a PLL to provide the clock, but it doesn't seem to compile with the PLL.

Thank you for your help. I created the Archive .qar file and attached it.