Can't set LoanIO by FPGA ,cycloneVsoc Dev kit
Hi,
There is a IDC 2*7 on the board, the pins are HPS pins,here is the schematic
Most of them are connnected to the HPS Bank7.
In HPS settings, I set the GPIO 58,59,60 as loanIOs(5,7 & 6 of the J32).
I set the IOs as output of the FPGA, and want to control them in my top layer
HPS setting
Top layer setting
Quartus setting
physical connnection(locations are checked correct)
Result of the pin, should be test_pulse,which is 0.
but no matter how I set them, they can't respond.
The boot method is baremetal SPL boot, I dont know whether it will influence the useage.
Reguards
Alex
Hi,
thanks for the reply , problem is solved, I sent the 313MHZ signal instead of 313KHZ, the GPIO pin with 3.3 LVTTL std dont have such high bandwidth.
When I set to 313KHZ the result is good.
Reguards
Alex