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CAlex's avatar
CAlex
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2 years ago
Solved

Can't set LoanIO by FPGA ,cycloneVsoc Dev kit

Hi, There is a IDC 2*7 on the board, the pins are HPS pins,here is the schematic Most of them are connnected to the HPS Bank7. In HPS settings, I set the GPIO 58,59,60 as loanIOs(5,7 ...
Board Debug
Fpga Devkit
  • CAlex's avatar
    CAlex
    1 year ago

    Hi,

    thanks for the reply , problem is solved, I sent the 313MHZ signal instead of 313KHZ, the GPIO pin with 3.3 LVTTL std dont have such high bandwidth.

    When I set to 313KHZ the result is good.

    Reguards

    Alex

CAlex's avatar
CAlex
Icon for Contributor rankContributor
2 years ago

Update:

If you are using the same dev kit and facing the same problem as I do,

please check the following setting: HPS sysmgr reg on LOANIO and GENERALIO settings.

If the J31 jumper is shorted.(So that my pins above can be connected to the HPS board).

With the old problem solved, a new problem occurred.

I set the LOANIO 60 as output and assigned it as a clk output(320KHz), yet through Oscilloscope I got a analog signal, which shocked me.

I changed the duty and the output changed with that, so the code has no problem.

But what I want is the digital signal.