Forum Discussion
Honored ContributorAudio CODEC AIC23 vhdl/verilog
Hello, We have a Altera EP2S60 development board (http://www.altera.com/products/devkits/altera/kit-dsp-2s60.html) , which has a Stratix II FPGA and AIC23 Audio CODEC. Altera does not have any controller or IP for controlling this audio codec. I am just wondering does any of you guys have any Verilog/VHDL example codes to control this audio codec. If you do not have then could you please direct me somewhere from where I will be able to get it. Your help would be highly appreciated. Thanks.
29 Replies
Altera_ForumHi pluhadia,
I have no idea how you synthesize the behavioral code into hardware, but…. If you set coeffs[32] = { 1, 0,0,…..0}; // all zero except for the first element How does it work?- Altera_Forum
Hi pluhadia,
I’ve missed “posedge” in registering dac_data in top.v. Latches are inferrd instead of registers. This may cause timing problem in your design. Please add “posedge” at always line: // Play back input data wire adc_dac_enable; always @( posedge clk_in_40M) begin if (adc_dac_enable) begin dac_data_L <= adc_data_L; dac_data_R <= adc_data_R; end end - Altera_Forum
Hi EOFZ,
I am confused about what to connect to the input and output ports of the filter module. Should filter_input_port <= adc_data_L;and dac_data_L <= signal from filter output port; dac_data_R <= signal from filter output port; OR module_input_port <= adc_data_reg;and dac_data_L <= [31:16]signal from filter output port; dac_data_R <= [15:0] signal from filter ouput port; I appreciate your help. - Altera_Forum
Hi pluhadia,
Unfortunately, I don’t understand your behavioral design. What do these mean ? filter_input_port signal from filter output port adc_data_reg If you use VHDL or VerilogHDL, it is easy for me. Here is a sample 4-tap averaging FIR for left channel, which can be used in top.v. reg signed [15:0] tap1, tap2, tap3, tap4; reg signed [17:0] filter_out; always @(posedge clk_in_40M) begin if (adc_dac_enable) begin tap1 <= adc_data_L; tap2 <= tap1; tap3 <= tap2; tap4 <= tap3; filter_out <= tap1 + tap2 + tap3 + tap4 ; dac_data_L <= filter_out[17:2]; end end - Altera_Forum
what happens to R channel in the above 4-tap averaging filter design. To hear the filtered output in the real time implementation on hardware,
does R channel remain unconnected Or is it filtered the same way as L channel Or If I do dac_data_R <= adc_data_R; (pass it as such) - Altera_Forum
The sample code does nothing to R channel output(dac_dagt_R) to simplify and shorten the code.
To sound R channel, please add another filter for dac_data_R, or connect adc output directly, etc., … what ever you want to hear. - Altera_Forum
I can hear the filtered output but it is accompanied with a lot of noise. Is the noise caused by: mistiming of signals or filter operation
- Altera_Forum
Hi pluhadia,
I don't hear any nosie. The problem may be in your hardware or design. 1. Which devkit do you use? 2. Can you hear clear sound with the original top.v? - Altera_Forum
I figured out the noise problem, I didn't use "signed" reg for the following, using unsigned reg was causing the noise, though I don't understand why it should happen.
reg signed [15:0] tap1, tap2, tap3, tap4; reg signed [17:0] filter_out; - Altera_Forum
Without signed keyword, you must extend sign bit by yourself for signed adder. Please refer to VelilogHDL text book for more detail.
reg [15:0] tap1, tap2, tap3, tap4; reg [17:0] filter_out; always @(posedge clk_in_40M) begin if (adc_dac_enable) begin tap1 <= adc_data_L; tap2 <= tap1; tap3 <= tap2; tap4 <= tap3; filter_out <= { {2{tap1[15]}}, tap1} + { {2{tap2[15]}}, tap2} + { {2{tap3[15]}}, tap3} + { {2{tap4[15]}}, tap4} ; dac_data_L <= filter_out[17:2]; end end
