Audio CODEC AIC23 vhdl/verilog

Without signed keyword, you must extend sign bit by yourself for signed adder. Please refer to VelilogHDL text book for more detail.

reg [15:0] tap1, tap2, tap3, tap4;

reg [17:0] filter_out;

always @(posedge clk_in_40M) begin

if (adc_dac_enable) begin

tap1 <= adc_data_L;

tap2 <= tap1;

tap3 <= tap2;

tap4 <= tap3;

filter_out <= { {2{tap1[15]}}, tap1} + { {2{tap2[15]}}, tap2} +

{ {2{tap3[15]}}, tap3} + { {2{tap4[15]}}, tap4} ;

dac_data_L <= filter_out[17:2];

end

end