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Altera_Forum
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17 years ago

Audio CODEC AIC23 vhdl/verilog

Hello, We have a Altera EP2S60 development board (http://www.altera.com/products/devkits/altera/kit-dsp-2s60.html) , which has a Stratix II FPGA and AIC23 Audio CODEC. Altera does not have any contro...
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Altera_Forum
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17 years ago

Hi EOFZ,

I am confused about what to connect to the input and output ports of the filter module. Should

filter_input_port <= adc_data_L;and

dac_data_L <= signal from filter output port;

dac_data_R <= signal from filter output port;

OR

module_input_port <= adc_data_reg;and

dac_data_L <= [31:16]signal from filter output port;

dac_data_R <= [15:0] signal from filter ouput port;

I appreciate your help.