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Honored Contributor
Honored ContributorAudio CODEC AIC23 vhdl/verilog
Hello, We have a Altera EP2S60 development board (http://www.altera.com/products/devkits/altera/kit-dsp-2s60.html) , which has a Stratix II FPGA and AIC23 Audio CODEC. Altera does not have any contro...
Altera_ForumHonored Contributor
Honored ContributorHi pluhadia,
I’ve missed “posedge” in registering dac_data in top.v. Latches are inferrd instead of registers. This may cause timing problem in your design. Please add “posedge” at always line: // Play back input data wire adc_dac_enable; always @( posedge clk_in_40M) begin if (adc_dac_enable) begin dac_data_L <= adc_data_L; dac_data_R <= adc_data_R; end end
