Audio CODEC AIC23 vhdl/verilog

Hi pluhadia,

I’ve missed “posedge” in registering dac_data in top.v. Latches are inferrd instead of registers. This may cause timing problem in your design. Please add “posedge” at always line:

// Play back input data

wire adc_dac_enable;

always @( posedge clk_in_40M) begin

if (adc_dac_enable) begin

dac_data_L <= adc_data_L;

dac_data_R <= adc_data_R;

end

end