Audio CODEC AIC23 vhdl/verilog

Hi pluhadia,

Unfortunately, I don’t understand your behavioral design. What do these mean ?

filter_input_port

signal from filter output port

adc_data_reg

If you use VHDL or VerilogHDL, it is easy for me. Here is a sample 4-tap averaging FIR for left channel, which can be used in top.v.

reg signed [15:0] tap1, tap2, tap3, tap4;

reg signed [17:0] filter_out;

always @(posedge clk_in_40M) begin

if (adc_dac_enable) begin

tap1 <= adc_data_L;

tap2 <= tap1;

tap3 <= tap2;

tap4 <= tap3;

filter_out <= tap1 + tap2 + tap3 + tap4 ;

dac_data_L <= filter_out[17:2];

end

end