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Altera_Forum
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17 years ago

Audio CODEC AIC23 vhdl/verilog

Hello, We have a Altera EP2S60 development board (http://www.altera.com/products/devkits/altera/kit-dsp-2s60.html) , which has a Stratix II FPGA and AIC23 Audio CODEC. Altera does not have any contro...
Altera_Forum's avatar
Altera_Forum
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17 years ago

I figured out the noise problem, I didn't use "signed" reg for the following, using unsigned reg was causing the noise, though I don't understand why it should happen.

reg signed [15:0] tap1, tap2, tap3, tap4;

reg signed [17:0] filter_out;