Occasional ContributorATX pll Reconfiguration not changing clock frequency
Hi, @JohnT_Intel @Sethuraman_K_Intel @Rahul_S_Intel1
I am using stratix 10 dev kit, in my project my requirement needs to use ATX PLL reconfiguration.
Single atx pll with 3 different clocks it should generate,i have enabled dynamic reconfiguration and embedded streamer and enabled multiple profiles,
stored 3 different profiles.
In simulation i am getting constant single frequency after selecting other profile using Register read modified write.
I am attaching the project data in zip format.
please check simulation and help me where i am going wrong.
Regards,
Rajesh
Hi,
Thanks for your update and sharing of the Modelsim simulation screenshot. For your information, as per the S10 L/H-Tile user guide, prior to reconfiguring ATX PLL, you would need to set the pre_reconfig bit -> return bus to PreSICE -> wait for pll_cal_busy to go low -> request bus from PreSICE -> initiate the embedded streamer.
Also, I notice that in your write data to the embedded streamer, the 540[7] bit is not written as 1. You would need to write this bit to 1 to initiate the streaming. You may refer to the section "A.1.4. Embedded Streamer" in the user guide for further details.
You may also refer to the following sections in the user guide
1. "Embedded Reconfiguration Streamer"
2. "Native PHY IP or PLL IP Core Guided Reconfiguration Flow"
Please let me know if there is any concern. Thank you.
