Forum Discussion
Occasional ContributorATX pll Reconfiguration not changing clock frequency
Hi,
Thanks for your update and sharing of the Modelsim simulation screenshot. For your information, as per the S10 L/H-Tile user guide, prior to reconfiguring ATX PLL, you would need to set the pre_reconfig bit -> return bus to PreSICE -> wait for pll_cal_busy to go low -> request bus from PreSICE -> initiate the embedded streamer.
Also, I notice that in your write data to the embedded streamer, the 540[7] bit is not written as 1. You would need to write this bit to 1 to initiate the streaming. You may refer to the section "A.1.4. Embedded Streamer" in the user guide for further details.
You may also refer to the following sections in the user guide
1. "Embedded Reconfiguration Streamer"
2. "Native PHY IP or PLL IP Core Guided Reconfiguration Flow"
Please let me know if there is any concern. Thank you.
Regular ContributorHi,
For your information, generally you would only need to use more than one refclk frequency if your target data rate cannot be derived using a single refclk frequency. If your target data rate A and B can be achieved using same refclk, then you can use a single refclk.
After you change this, run through a simulation. If it is still not working, please share with me the screenshot showing the ATX PLL reconfig interface registers writing steps and sequence to see if can spot any anomaly. You can share me the simulation files as well.
Please let me know if there is any concern. Thank you.
Occasional ContributorHi @CheePin_C_Intel ,
As per your suggestion, as same reference clock can generate 3 frequencies
so RTL is modified.
please see the modelsim snapshots too,
i am writing other profile to load but the output tx clock is same through out the simulation.
please suggest where my design is going wrong
Regards,
Rajesh
