Forum Discussion
Occasional ContributorATX pll Reconfiguration not changing clock frequency
Hi,
Thanks for your update and sharing of the Modelsim simulation screenshot. For your information, as per the S10 L/H-Tile user guide, prior to reconfiguring ATX PLL, you would need to set the pre_reconfig bit -> return bus to PreSICE -> wait for pll_cal_busy to go low -> request bus from PreSICE -> initiate the embedded streamer.
Also, I notice that in your write data to the embedded streamer, the 540[7] bit is not written as 1. You would need to write this bit to 1 to initiate the streaming. You may refer to the section "A.1.4. Embedded Streamer" in the user guide for further details.
You may also refer to the following sections in the user guide
1. "Embedded Reconfiguration Streamer"
2. "Native PHY IP or PLL IP Core Guided Reconfiguration Flow"
Please let me know if there is any concern. Thank you.
Regular ContributorHi,
As I looked into your a.v, I notice that the 3 ATX PLL refclk inputs are connected to the same clock source:
atx1 atx1_inst (
.pll_refclk0 (pll_refclk1), // input, width = 1, pll_refclk0.clk
.pll_refclk1 (pll_refclk1), // input, width = 1, pll_refclk0.clk
.pll_refclk2 (pll_refclk1), // input, width = 1, pll_refclk0.clk
Not sure if they are something intended?
Thank you.
Rk_AthramHi,
As i want 3 different op frequencies,
i did not fount any example design, the example design i referred are stated
" to change clock frequency we have to change reference clk " -- Please clarify this statement
so i have taken 3 ref clks but given same frequency.
If it is possible to change dynamically change the speed using single reference clock ! then i will use single reference clock only.
