New ContributorArria10 FPGA's Emif Hard IP showing deviation in behavior from expected Avalon bridge protocol
Hi, we are using the Intel device kit DK-DEV-10AX115S-A with 10AX115S2F45I1SG FPGA device and HiLo DDR4 mounted on this. The FPGA design has a cortex core with AXI bridge integrated with Emif hard IP for DDR4 i/f. We have AXI <-> Avalon CDC bridge (generated by platform designer) to interface the core with Emif controller, where the core/AXI is running at a much lower freq compared to Emif's avalon i/f. We find that Emif controller’s Avalon bridge is not behaving as expected. This is the observation :- In the case of a single read transfer - waitrequest is asserted by Emif controller for multiple clock cycles during read, which is delaying the de-assertion of read. This is getting translated as multiple reads by the Emif controller and multiple reads to DDR4 are happening. Similar observations for a single write transaction also. Finally all these read data and readdatavalids are going back to AXI bus causing it to stall.
We are using the Quartus prime pro version 23.4
Please let us know if any more information is needed
Hi, this works : inverting the amm_ready from EMIF
thanks for the help!
