Arria10 FPGA's Emif Hard IP showing deviation in behavior from expected Avalon bridge protocol

Hi, we are using the Intel device kit DK-DEV-10AX115S-A with 10AX115S2F45I1SG FPGA device and HiLo DDR4 mounted on this. The FPGA design has a cortex core with AXI bridge integrated with Emif hard ...