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dpk23's avatar
dpk23
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1 year ago
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Arria10 FPGA's Emif Hard IP showing deviation in behavior from expected Avalon bridge protocol

Hi, we are using the Intel device kit DK-DEV-10AX115S-A with 10AX115S2F45I1SG FPGA device and HiLo DDR4 mounted on this. The FPGA design has a cortex core with AXI bridge integrated with Emif hard ...
Fpga Devkit
  • dpk23's avatar
    dpk23
    1 year ago

    Hi, this works : inverting the amm_ready from EMIF

    thanks for the help!

sstrell's avatar
sstrell
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1 year ago

This doesn't make sense (and you're not showing the waitrequest signal in question). If waitrequest is asserted, control signals must continue to be asserted until 1 clock cycle after waitrequest is deasserted. If you are holding the read signal past this point, then yes, multiple reads will occur.

I'm assuming these are the signals at the EMIF. You should also look at the signals on the other side, whatever is issuing the commands.

dpk23's avatar
dpk23
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1 year ago

Hi, the waitrequest is same as amm_ready

I have attached snapshot of avalon read/write protocol as per spec - for a single data transfer

The read (along with other control signals) is delayed as long as the waitrequest is asserted

The commands issues from master side follow the protocol, i.e. as long as amm_read/waitrequest is asserted the control signals dont change.

But the EMIF is sending multiple readdatavalids - instead of just 1 - and also even before the amm_read/waitrequest is de-asserted