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dpk23's avatar
dpk23
Icon for New Contributor rankNew Contributor
2 years ago
Solved

Arria10 FPGA's Emif Hard IP showing deviation in behavior from expected Avalon bridge protocol

Hi, we are using the Intel device kit DK-DEV-10AX115S-A with 10AX115S2F45I1SG FPGA device and HiLo DDR4 mounted on this. The FPGA design has a cortex core with AXI bridge integrated with Emif hard ...
Fpga Devkit
  • dpk23's avatar
    dpk23
    2 years ago

    Hi, this works : inverting the amm_ready from EMIF

    thanks for the help!

sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
2 years ago

So the IP is naming the signal wrong (compared to the Avalon spec) and inverting its function without any details. Wow.

Glad it's working for you.