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As I can see from ADC EVM schematic, SPI lines on the output connector (SEN, SDATA, SCLK) are normally left floating on the board and one can choose to use them installing some resistors. So I should have no problem there since I can still communicate with SPI via USB connection, as the board permits to do.
There are HSMC_D1 and HSMC_D2 left. HSMC_D1 is another SPI bus signal, used by a component on the TI board which I don't need to use (it can be isolated from the power supply by removing a jumper), so it shouldn't be a problem either. The only signal I need to use is on HSMC_D2, which is still connected to FPGA BANK 5 and carries an over-range output bit coming directly from ADC. Voltage levels for this ADC logic output are: VOH = 1.7 V and VOL = 0.1 V.
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This all sounds good. You should have no trouble connecting the two boards.
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So here's my first question: I've already set HSMC_VCCIO = 2.5 V for using LVDS. This setting has effect for all BANK 5 and BANK 6 pins, right?
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Yes; look at p25 of the DE115 schematic HSMC_VCCIO powers bank 5 and 6.
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So for HSMC LVCMOS lines (from Cyclone IV datasheet p.12) it has to be: VIL = 0.7 V, VIH = 1.7 V. So I'm exactly on the threshold for the high logic state: is it going to be a problem without any solution?
Actually, the same OVR signal from EVM board is repeated (can't understand why, maybe I'll ask to TI forum) on another output connector pin, which becomes INPUT3_M signal on HSMC connector: it is still the same 1.8 LVCMOS output, but it is carried on a single LVDS line. I think I won't need it, since I would have here the same situation I had on HSMC_D2, but is it going to be a problem having this undesired signal on INPUT3_M?
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DE115 schematic p23 shows that the single-ended signals come from bank 5, so they are 2.5V LVCMOS.
From your comments, I assume the TI driver signals are 1.8V LVCMOS.
Even though these two logic standards are not directly compatible, these voltages look compatible "enough". Plug the signals together and see if things work. If they don't, you know what the problem is, so you can then figure out a better solution. Since the TI device is driving to an FPGA input, you can't damage anything ... if it was the 2.5V driver driving a 1.8V receiver, then I would be a little more careful.
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Lastly, a curiosity: if I needed to use the LVCMOS signal on INPUT_3M line, would I be able to do it? Or else, can I independently program each pin of my Cyclone IV linked to HSMC connector to be LVDS or LVCMOS?
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There's a couple of potential issues;
1) Quartus might not let you.
There are limitations as to what single-ended signals can be located next to LVDS signals. You'd have to try P&R to see if Quartus will let you.
2) It depends if you have installed the LVDS terminations.
INPUT_3M on the adapter board goes to an LVDS pin on the DE115. If you install the 100-ohm termination resistors on the DE115 board, then you essentially connect pairs of pins together as far as single-ended signals go. You could drive a single-ended signal on INPUT_3M, and tri-state INPUT_3P, but the signal driven on INPUT_3M would appear on INPUT_3P back at its source. If INPUT_3P is just dangling, and the signal on INPUT_3P was not too fast (since you would get coupling and reflections), then it might work ok.
If you examine the schematics, and figure out that you are not going to short pins out, you can then just 'try it'. If your idea works, and its good enough to get your test completed, just go for it. Later when you design a system, you can take a little more care. Just keep in mind that prototyping is prototyping; you're allowed to violate the rules ... just so long as you are aware you are violating them.
Cheers,
Dave
Honored Contributor
