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I'm attaching the TI adapter and EVM schematics
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Ok, thanks.
So from their adapter board schematic, you can see that the connections to the HSMC;
* 16-bit LVDS data and two LVDS clocks.
* some single-ended signals to HSMC_D0, 1, and D2 on the DE115 HSMC connector. You'll need to check those logic levels, and their direction.
* some single-ended signals to HSMC_SCL,SDA - you'll also need to check those logic levels, and their direction. The DE115 board uses these signals for I2C, whereas from the TI names I suspect SPI. You need to be careful that the TI board is not expecting to drive these signals, since the DE115 device will too. If both devices were I2C, this would be ok, since I2C is open-drain. However, if the TI device is thinking an SPI slave is on those wires, then it can drive active high, and if the FPGA or an I2C device on the DE115 drives active low, you might damage the device.
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On DE2-115 schematic p27, I can see how HSMC_VCCIO is set: does this setting have influence on LVDS transmission or is it only for LVCMOS?
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It must be 2.5V for LVDS.
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I've got also another question: on the same page I can see a set of resistors between each pair of Rx lines, as they're needed for LVDS to work properly (they should be 100 ohm resistors, right?). What does DNI stand for? Is it for "Do Not Install"? Should I care about it?
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p23 you mean?
You would need to check whether the Cyclone device support on-chip 100-Ohm termination. If it did, then I would not expect to see these external resistors ... so there is a good chance you
need these resistors for LVDS operation. DNI does mean 'do not install', so you will need to install the resistors.
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TI ADS58B19EVM board uses LVDS section pins as LVDS lines: if I got the problem, I should then verify common and differential mode signal on these lines. The ADC LVDS output lines come directly on the connector of the EVM board, so if I don't go wrong I have to look at the ADC datasheet.
I can find there a LVDS output of +/- 350 mV with a common mode 0.85 V < VCM < 1.25 V. On the Cyclone IV datasheet (p14) I can find LVDS input requirements of minimum 100 mV differential and an overall common mode range of 0.05 V - 1.55 V (actually it changes with operating speed, but I think the slowest speed of 500 Mbps should be already sufficient for me), so it should be okay. Does it make sense or I'm missing something?
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No, you did not miss anything, you've done that analysis nicely. The ADC and FPGA are defining their interface as 'LVDS' which means they are both adhering to the LVDS logic standard, so you can DC couple them without issues. The potential issue you could face would be that if your ADC LVDS goes above 800Mbps, the Cyclone might not be able to work, but for 500Mbps, you should be ok.
Even though the LVDS connections are logically compatible, you will still need to check the single-ended signals. Go back to the DE115 schematic, and find out the VCCIO of the HSMC single-ended signals. Then check there will be no driver conflicts with the SPI/I2C signals.
Cheers,
Dave
Honored Contributor
