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ove's avatar
ove
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2 months ago

Agilex5 Eagle ES, NIOS-V + TSE IP

Trying to setup a NIOS-V with a TSE MAC to utilize the ethernet interface connected to the FPGA on the Agilex Eagle ES devkit.

NIOS executes firmware and able to read the PHY registers. But when connecting the ethernet cable nothing seems to happen, status registers does not change and no link-up is reported. 

Does anyone know of any examples using the NIOS-V and TSE with RGMII interface that I can look at to troubleshoot the issue ?

Fpga Devkit
soc devkit

5 Replies

  • SteveK_Arrow's avatar
    SteveK_Arrow
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    2 months ago

    Hi ove

    There are no examples available on the Eagle board at present. However, I did find this example for the Altera development kit that could be ported. It uses FreeRTOS to manage the Ethernet stack and TSE IP with an RGMII interface to a Marvel phy.

    https://github.com/altera-fpga/agilex5e-nios-ed/blob/rel/25.3.1/niosv_g/niosv_g_webserver_ping/docs/Nios_Vg_Processor_Webserver_Ping_Design_on_Agilex_5_FPGA.md

    Regards

    Steven

    • ove's avatar
      ove
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      2 months ago

      Hi SteveK_Arrow​ 

      Thanks for the link, I will check it out.

      Another strange thing is that I scoped the XTAL_I/CLK_IN/REF_CLK pin of U33, and it seems to be only 12.5Mhz. The source of this clock is U2 which is connected to the HPS. Not sure why this outputs only 12.5 and not 25.... Might be that it requires some initialization prior in order for both of the PHYs to function ?

      Was thinking about mounting R279 and removing R379 just to test the theory.. But hoping to avoid it :)

  • Naji_Naufel_Arrow's avatar
    Naji_Naufel_Arrow
    Icon for Occasional Contributor rankOccasional Contributor
    2 months ago

    Hi ove,

    Are you running an RTSO, or OS with a TCP/IP stack to communicate with the TSE?

    If not, How are you trying to access the TSE from the NIOS?

     

    Thank you

     

    • ove's avatar
      ove
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      2 months ago

      Hi Naji_Naufel_Arrow​ 

      Using the functions included in the BSP (#include "intel_eth_tse_regs.h") right now just for testing 

      • tehjingy_Altera's avatar
        tehjingy_Altera
        Icon for Regular Contributor rankRegular Contributor
        1 month ago

        Hi ove 

         

        You could take a look at the ED NiosV +TSE IP in the link below:

        https://altera-fpga.github.io/rel-25.3/embedded-designs/agilex-5/e-series/premium/niosv/niosv_g/webserver_ping/ug-webserver-ping-agx5e-premium/#nios-vg-ping-application-litert-design-architecture