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ove's avatar
ove
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5 months ago

Agilex5 Eagle ES, NIOS-V + TSE IP

Trying to setup a NIOS-V with a TSE MAC to utilize the ethernet interface connected to the FPGA on the Agilex Eagle ES devkit. NIOS executes firmware and able to read the PHY registers. But when con...
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SteveK_Arrow's avatar
SteveK_Arrow
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4 months ago

Hi ove

There are no examples available on the Eagle board at present. However, I did find this example for the Altera development kit that could be ported. It uses FreeRTOS to manage the Ethernet stack and TSE IP with an RGMII interface to a Marvel phy.

https://github.com/altera-fpga/agilex5e-nios-ed/blob/rel/25.3.1/niosv_g/niosv_g_webserver_ping/docs/Nios_Vg_Processor_Webserver_Ping_Design_on_Agilex_5_FPGA.md

Regards

Steven

  • ove's avatar
    ove
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    4 months ago

    Hi SteveK_Arrow​ 

    Thanks for the link, I will check it out.

    Another strange thing is that I scoped the XTAL_I/CLK_IN/REF_CLK pin of U33, and it seems to be only 12.5Mhz. The source of this clock is U2 which is connected to the HPS. Not sure why this outputs only 12.5 and not 25.... Might be that it requires some initialization prior in order for both of the PHYs to function ?

    Was thinking about mounting R279 and removing R379 just to test the theory.. But hoping to avoid it :)