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The high-speed transceiver lanes on the HSMC are not connected.
If the TI board uses the transceiver lanes, then this board would not be useful to you.
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On the HSMC specifications I could find trainscever lanes and only now I'm sure my TI adapter board doesn't use them (I'm attaching the TI adapter and EVM schematics).
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If you look on p27 of the schematic, you will see that VCCIO for the HSMC connector can be set using a jumper. If the TI EVM board HSMC connector uses the pins in the LVDS section of the connector, then you need to check whether the FPGA needs to interface using 2.5V LVDS or 1.5/1.8/2.5/3.3V LVCMOS.
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On DE2-115 schematic p27, I can see how HSMC_VCCIO is set: does this setting have influence on LVDS transmission or is it only for LVCMOS?
I've got also another question: on the same page I can see a set of resistors between each pair of Rx lines, as they're needed for LVDS to work properly (they should be 100 ohm resistors, right?). What does DNI stand for? Is it for "Do Not Install"? Should I care about it?
TI ADS58B19EVM board uses LVDS section pins as LVDS lines: if I got the problem, I should then verify common and differential mode signal on these lines. The ADC LVDS output lines come directly on the connector of the EVM board, so if I don't go wrong I have to look at the ADC datasheet.
I can find there a LVDS output of +/- 350 mV with a common mode 0.85 V < VCM < 1.25 V. On the Cyclone IV datasheet (p14) I can find LVDS input requirements of minimum 100 mV differential and an overall common mode range of 0.05 V - 1.55 V (actually it changes with operating speed, but I think the slowest speed of 500 Mbps should be already sufficient for me), so it should be okay. Does it make sense or I'm missing something?
Regards,
Lorenzo
Honored Contributor
