[Agilex]:Error Sending Bitstream..!!

Hello Raju Satrasala,

I understand that you're facing issues with the Agilex 7 F-Series SOC Development Kit during the Linux boot-up process when using the provided prebuilt binaries for the PCIe Root Port reference design.

The error messages you've encountered suggest problems with the FPGA image or other script failures. Let's try to troubleshoot the issue:

FPGA Image Check:

• Verify that the FPGA image you're trying to load is not corrupted. Make sure it was built and programmed correctly. Check the bitstream file and its integrity.

SD Card Check:

• Ensure the SD card is properly inserted, and the files on it are not corrupted. You may want to reformat the SD card and copy the necessary files onto it again.

Boot Sequence:

• Double-check the boot sequence and configuration settings in the board's U-Boot environment. Ensure that the SD card is set as the primary boot device.

File Paths:

• The "Unable to read file /" error suggests that the bootloader can't find the necessary files. Verify that the file paths in your boot script are correctly configured.

Script and Environment Variables:

• Review the boot script and environment variables in U-Boot to make sure they are set up correctly. Ensure that the script points to the right locations for the FPGA image and other essential files.

If you have performed all the suggested tests and ensure that the file that you downloaded from Rocketboard is no problem, please talk with the developer.

I saw there is an open forum page in RocketBoard forum https://forum.rocketboards.org/t/agilex-error-sending-bitstream/3273 file by you as well.

Regards,

Wincent_Intel

Hi,

I wish to follow up with you about this case.

Do you have any further questions on this matter ?

​​​​​​​Else I would like to have your permission to close this forum ticket

Regards,

Wincent_Intel

p/s: If any answer from the community or Intel Support is helpful, please feel free to give the best answer or rate 9/10 survey.

Hi @Wincent_Altera ,

Thank you for your response.

We are utilizing the default wic image from the Intel Agilex® 7 FPGA F-Series SoC binaries archive for SD-Card booting.

However, we are still encountering the error mentioned earlier.

Thanks & Regards

Raju Satrasala

Hi @Wincent_Altera ,

Thank you for your response, but it appears our issue remains unresolved. Please find the attached log for reference.

I have attached a log file for your reference. Please review it and let me know what steps to take next to address our issue.

Thanks & Regards

Satrasala Raju

Hi @Wincent_Altera ,

Please find the below table for reference

Rocket Board Agilex SOC

https://www.rocketboards.org/foswiki/Documentation/agilexSoCGSRD

Rocket Board PCI RP

Agilex PCIe Root Port | Documentation | RocketBoards.org

We attempted to utilize the Rocket Board PCI RP Switch Configuration, but encountered issues with detecting the JTAG Chain. However, when we employed the Agilex EVM Working Switch Configuration, we were able to successfully detect the JTAG Chain.

Thanks & Regards

Satrasala Raju

Hi @Wincent_Altera ,

Thank you for your response.

I have attempted to resolve the issue by re-downloading the SD Card Image, but unfortunately, I continue to face the same problem.

Is it possible for you to provide the example design files along with detailed building steps for Linux and U-Boot?

Thanks & Regards

Raju Satrasala

Hi @Wincent_Altera ,

Thanks for your response.

Please check the below query once and let me know how to solve it.

Compilation Error in Quartus Prime 23.3 for Agilex PCIe Root Port Design Example - Intel Community

Thanks & Regards

Raju Satrasala